mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
131 lines
4.5 KiB
C
131 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/* *I*** - Covers boot page */
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
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!defined(CONFIG_SECURE_BOOT)
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/*
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* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
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* SRAM is at 0xfffc0000, it covered the 0xfffff000.
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_256K, 1),
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#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
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/*
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* *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
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* the physical address of the SRAM is at 0xbffc0000,
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* and virtual address is 0xfffc0000
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
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CONFIG_SYS_INIT_L3_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_256K, 1),
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#else
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_4K, 1),
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#endif
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_16M, 1),
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/* *I*G* - Flash, localbus */
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/* This will be changed to *I*G* after relocation to RAM. */
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_256M, 1),
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#ifndef CONFIG_SPL_BUILD
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 3, BOOKE_PAGESZ_1G, 1),
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/* *I*G* - PCI I/O */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_256K, 1),
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/* Bman/Qman */
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#ifdef CONFIG_SYS_BMAN_MEM_PHYS
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SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 5, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
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CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_16M, 1),
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#endif
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#ifdef CONFIG_SYS_QMAN_MEM_PHYS
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SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 7, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
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CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 8, BOOKE_PAGESZ_16M, 1),
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#endif
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#endif
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 9, BOOKE_PAGESZ_4M, 1),
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#endif
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#ifdef CONFIG_SYS_NAND_BASE
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/*
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* *I*G - NAND
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* entry 14 and 15 has been used hard coded, they will be disabled
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* in cpu_init_f, so we use entry 16 for nand.
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 10, BOOKE_PAGESZ_64K, 1),
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#endif
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#ifdef CONFIG_SYS_CPLD_BASE
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SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 11, BOOKE_PAGESZ_256K, 1),
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#endif
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#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
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0, 12, BOOKE_PAGESZ_1G, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
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CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
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0, 13, BOOKE_PAGESZ_1G, 1)
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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