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u-boot/doc/device-tree-bindings/clock
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Patrick Delaunay bbd108a082 clk: stm32mp1: correctly handle Clock Spreading Generator 
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
..
microchip,pic32-clock.txt
nvidia,tegra20-car.txt
rockchip,rk3188-cru.txt
rockchip,rk3288-cru.txt
rockchip,rk3288-dmc.txt
rockchip,rk3368-dmc.txt rockchip: rk3368: add DRAM controller driver with DRAM initialisation 2017-08-13 17:12:33 +02:00
rockchip,rk3399-dmc.txt rockchip: arm64: rk3399: add ddr controller driver 2017-03-16 16:03:45 -06:00
rockchip.txt
snps,hsdk-cgu.txt ARC: clk: introduce HSDK CGU clock driver 2017-12-11 11:36:23 +03:00
st,stm32-rcc.txt clk: stm32f7: add clock driver for stm32f7 family 2017-03-17 14:15:12 -04:00
st,stm32h7-rcc.txt dm: clk: add clk driver support for stm32h7 SoCs 2017-09-22 07:40:01 -04:00
st,stm32mp1.txt clk: stm32mp1: correctly handle Clock Spreading Generator 2019-02-09 07:50:57 -05:00
ti,sci-clk.txt clk: Introduce TI System Control Interface (TI SCI) clock driver 2018-09-11 08:32:55 -04:00