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337bc26f05
The NPCM driver can use on npcm7xx/npcm8xx so add npcm8xx header for driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
53 lines
1.8 KiB
C
53 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_AES_H_
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#define _NPCM_AES_H_
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#define AES_OP_ENCRYPT 0
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#define AES_OP_DECRYPT 1
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#define SIZE_AES_BLOCK (AES128_KEY_LENGTH)
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struct npcm_aes_regs {
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unsigned char reserved_0[0x400]; // 0x000
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unsigned int aes_key_0; // 0x400
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unsigned int aes_key_1; // 0x404
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unsigned int aes_key_2; // 0x408
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unsigned int aes_key_3; // 0x40c
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unsigned char reserved_1[0x30]; // 0x410
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unsigned int aes_iv_0; // 0x440
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unsigned char reserved_2[0x1c]; // 0x444
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unsigned int aes_ctr_0; // 0x460
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unsigned char reserved_3[0x0c]; // 0x464
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unsigned int aes_busy; // 0x470
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unsigned char reserved_4[0x04]; // 0x474
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unsigned int aes_sk; // 0x478
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unsigned char reserved_5[0x14]; // 0x47c
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unsigned int aes_prev_iv_0; // 0x490
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unsigned char reserved_6[0x0c]; // 0x494
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unsigned int aes_din_dout; // 0x4a0
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unsigned char reserved_7[0x1c]; // 0x4a4
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unsigned int aes_control; // 0x4c0
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unsigned int aes_version; // 0x4c4
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unsigned int aes_hw_flags; // 0x4c8
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unsigned char reserved_8[0x28]; // 0x4cc
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unsigned int aes_sw_reset; // 0x4f4
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unsigned char reserved_9[0x08]; // 0x4f8
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unsigned int aes_fifo_data; // 0x500
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unsigned char reserved_10[0xfc]; // 0x504
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unsigned int aes_fifo_status; // 0x600
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};
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#define AES_BUSY_BIT BIT(0)
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#define SW_RESET_BIT BIT(0)
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#define AES_SK_BIT BIT(0)
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#define DIN_FIFO_FULL BIT(0)
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#define DIN_FIFO_EMPTY BIT(1)
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#define DOUT_FIFO_FULL BIT(2)
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#define DOUT_FIFO_EMPTY BIT(3)
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#define DIN_FIFO_OVERFLOW BIT(4)
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#define DOUT_FIFO_UNDERFLOW BIT(5)
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int npcm_aes_select_key(u8 fkeyind);
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#endif
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