mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
501be47032
Pull the PL310 clearing code into common code, so it can be reused by Arria10. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
45 lines
968 B
C
45 lines
968 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (C) 2016-2017 Intel Corporation
|
|
*/
|
|
|
|
#ifndef _MISC_H_
|
|
#define _MISC_H_
|
|
|
|
#include <asm/sections.h>
|
|
|
|
void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
|
|
|
|
struct bsel {
|
|
const char *mode;
|
|
const char *name;
|
|
};
|
|
|
|
extern struct bsel bsel_str[];
|
|
|
|
#ifdef CONFIG_FPGA
|
|
void socfpga_fpga_add(void *fpga_desc);
|
|
#else
|
|
inline void socfpga_fpga_add(void *fpga_desc) {}
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
|
|
void socfpga_sdram_remap_zero(void);
|
|
static inline bool socfpga_is_booting_from_fpga(void)
|
|
{
|
|
if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
|
|
(__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
|
|
return true;
|
|
return false;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
|
|
void socfpga_init_security_policies(void);
|
|
void socfpga_sdram_remap_zero(void);
|
|
#endif
|
|
|
|
void do_bridge_reset(int enable, unsigned int mask);
|
|
void socfpga_pl310_clear(void);
|
|
|
|
#endif /* _MISC_H_ */
|