mirror of
https://github.com/AsahiLinux/u-boot
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4a41a1a6f0
We will generate DRAM 4000MT/s as default for i.MX8MP. So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
194 lines
3.9 KiB
C
194 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/lpddr4_define.h>
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static inline void poll_pmu_message_ready(void)
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{
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unsigned int reg;
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do {
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reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
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} while (reg & 0x1);
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}
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static inline void ack_pmu_message_receive(void)
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{
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unsigned int reg;
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reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
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do {
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reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
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} while (!(reg & 0x1));
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reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
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}
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static inline unsigned int get_mail(void)
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{
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unsigned int reg;
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poll_pmu_message_ready();
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reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
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ack_pmu_message_receive();
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return reg;
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}
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static inline unsigned int get_stream_message(void)
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{
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unsigned int reg, reg2;
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poll_pmu_message_ready();
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reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
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reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
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reg2 = (reg2 << 16) | reg;
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ack_pmu_message_receive();
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return reg2;
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}
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static inline void decode_major_message(unsigned int mail)
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{
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debug("[PMU Major message = 0x%08x]\n", mail);
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}
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static inline void decode_streaming_message(void)
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{
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unsigned int string_index, arg __maybe_unused;
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int i = 0;
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string_index = get_stream_message();
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debug("PMU String index = 0x%08x\n", string_index);
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while (i < (string_index & 0xffff)) {
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arg = get_stream_message();
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debug("arg[%d] = 0x%08x\n", i, arg);
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i++;
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}
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debug("\n");
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}
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int wait_ddrphy_training_complete(void)
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{
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unsigned int mail;
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while (1) {
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mail = get_mail();
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decode_major_message(mail);
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if (mail == 0x08) {
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decode_streaming_message();
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} else if (mail == 0x07) {
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debug("Training PASS\n");
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return 0;
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} else if (mail == 0xff) {
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debug("Training FAILED\n");
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return -1;
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}
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}
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}
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void ddrphy_init_set_dfi_clk(unsigned int drate)
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{
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switch (drate) {
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case 4000:
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dram_pll_init(MHZ(1000));
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dram_disable_bypass();
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break;
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case 3200:
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dram_pll_init(MHZ(800));
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dram_disable_bypass();
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break;
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case 3000:
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dram_pll_init(MHZ(750));
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dram_disable_bypass();
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break;
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case 2400:
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dram_pll_init(MHZ(600));
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dram_disable_bypass();
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break;
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case 1600:
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dram_pll_init(MHZ(400));
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dram_disable_bypass();
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break;
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case 1066:
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dram_pll_init(MHZ(266));
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dram_disable_bypass();
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break;
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case 667:
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dram_pll_init(MHZ(167));
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dram_disable_bypass();
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break;
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case 400:
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dram_enable_bypass(MHZ(400));
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break;
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case 100:
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dram_enable_bypass(MHZ(100));
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break;
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default:
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return;
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}
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}
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void ddrphy_init_read_msg_block(enum fw_type type)
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{
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}
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void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
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unsigned int mr_data)
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{
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unsigned int tmp;
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/*
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* 1. Poll MRSTAT.mr_wr_busy until it is 0.
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* This checks that there is no outstanding MR transaction.
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* No writes should be performed to MRCTRL0 and MRCTRL1 if
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* MRSTAT.mr_wr_busy = 1.
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*/
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp & 0x1);
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/*
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* 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
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* (for MRWs) MRCTRL1.mr_data to define the MR transaction.
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*/
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reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
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reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
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reg32setbit(DDRC_MRCTRL0(0), 31);
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}
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unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
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{
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unsigned int tmp;
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reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
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do {
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tmp = reg32_read(DDRC_MRSTAT(0));
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} while (tmp & 0x1);
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reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
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reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
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reg32setbit(DDRC_MRCTRL0(0), 31);
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do {
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tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
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} while ((tmp & 0x8) == 0);
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tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
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tmp = tmp & 0xff;
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reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
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return tmp;
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}
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