mirror of
https://github.com/AsahiLinux/u-boot
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c4ee4fe92e
----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCY3IX9A8cc2JhYmljQGRl bnguZGUACgkQ9PVl5Jpo76a1dQCfTS1TpBF/Sjj0htkhw88AI+3x6UIAni5w6FmV bXA7Ymykew4cCkSRvesZ =OdkN -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx For 2022.01 ----------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14083 - Fix UART - moved to binman (MX8 boards) - Toradex: sync DTS with Linux - Gateworks: fixes - New boards : MSC SM2S iMX8MP
63 lines
1.6 KiB
C
63 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Based on vendor support provided by AVNET Embedded
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*
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* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
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* Copyright 2021 General Electric Company
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* Copyright 2021 Collabora Ltd.
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*/
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#ifndef __MSC_SM2S_IMX8MP_H
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#define __MSC_SM2S_IMX8MP_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_FEC_MXC_PHYADDR 1
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#define PHY_ANEG_TIMEOUT 20000
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#endif
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 2)
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#include <config_distro_bootcmd.h>
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"image=Image\0" \
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"console=ttymxc1,115200\0" \
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"fdt_addr_r=0x43000000\0" \
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"boot_fdt=try\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=1\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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/* Link Definitions */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
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#define PHYS_SDRAM_2 0xc0000000
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#define PHYS_SDRAM_2_SIZE 0x0
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#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
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#define CFG_SYS_FSL_USDHC_NUM 2
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#define CFG_SYS_FSL_ESDHC_ADDR 0
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#endif
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