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3a29afcbbf
Alignment with kernel directory name as it have already bindings for
DDR controllers in the directory:
Documentation/devicetree/bindings/memory-controller
PS: the drivers using RAM u-class should be associated with
this binding directory
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
58 lines
1.5 KiB
Text
58 lines
1.5 KiB
Text
ST, stm32 flexible memory controller Drive
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Required properties:
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- compatible : "st,stm32-fmc"
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- reg : fmc controller base address
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- clocks : fmc controller clock
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u-boot,dm-pre-reloc: flag to initialize memory before relocation.
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on-board sdram memory attributes:
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- st,sdram-control : parameters for sdram configuration, in this order:
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number of columns
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number of rows
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memory width
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number of intenal banks in memory
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cas latency
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read burst enable or disable
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read pipe delay
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- st,sdram-timing: timings for sdram, in this order:
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tmrd
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txsr
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tras
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trc
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trp
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trcd
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There is device tree include file at :
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include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
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parameters as MACROS.
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Example:
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fmc: fmc@A0000000 {
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compatible = "st,stm32-fmc";
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reg = <0xA0000000 0x1000>;
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clocks = <&rcc 0 64>;
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u-boot,dm-pre-reloc;
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};
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&fmc {
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pinctrl-0 = <&fmc_pins>;
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pinctrl-names = "default";
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status = "okay";
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/* sdram memory configuration from sdram datasheet */
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bank1: bank@0 {
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
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CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
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TRCD_18>;
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};
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/* sdram memory configuration from sdram datasheet */
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bank2: bank@1 {
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st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
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CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
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TRCD_18>;
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};
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}
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