mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-19 09:43:08 +00:00
f7ae49fc4f
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
249 lines
5.5 KiB
C
249 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <mmc.h>
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#include <spi_flash.h>
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#include <nand.h>
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#include <asm/arch/image.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#define MMC_DEV 0
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#define QSPI_DEV 1
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#define NAND_DEV 2
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#define QSPI_NOR_DEV 3
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static int __get_container_size(ulong addr)
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{
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struct container_hdr *phdr;
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struct boot_img_t *img_entry;
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struct signature_block_hdr *sign_hdr;
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u8 i = 0;
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u32 max_offset = 0, img_end;
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phdr = (struct container_hdr *)addr;
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if (phdr->tag != 0x87 && phdr->version != 0x0) {
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debug("Wrong container header\n");
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return -EFAULT;
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}
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max_offset = sizeof(struct container_hdr);
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img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr));
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for (i = 0; i < phdr->num_images; i++) {
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img_end = img_entry->offset + img_entry->size;
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if (img_end > max_offset)
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max_offset = img_end;
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debug("img[%u], end = 0x%x\n", i, img_end);
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img_entry++;
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}
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if (phdr->sig_blk_offset != 0) {
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sign_hdr = (struct signature_block_hdr *)(addr + phdr->sig_blk_offset);
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u16 len = sign_hdr->length_lsb + (sign_hdr->length_msb << 8);
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if (phdr->sig_blk_offset + len > max_offset)
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max_offset = phdr->sig_blk_offset + len;
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debug("sigblk, end = 0x%x\n", phdr->sig_blk_offset + len);
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}
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return max_offset;
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}
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static int get_container_size(void *dev, int dev_type, unsigned long offset)
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{
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u8 *buf = malloc(CONTAINER_HDR_ALIGNMENT);
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int ret = 0;
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if (!buf) {
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printf("Malloc buffer failed\n");
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return -ENOMEM;
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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if (dev_type == MMC_DEV) {
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unsigned long count = 0;
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struct mmc *mmc = (struct mmc *)dev;
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count = blk_dread(mmc_get_blk_desc(mmc),
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offset / mmc->read_bl_len,
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CONTAINER_HDR_ALIGNMENT / mmc->read_bl_len,
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buf);
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if (count == 0) {
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printf("Read container image from MMC/SD failed\n");
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return -EIO;
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}
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}
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#endif
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#ifdef CONFIG_SPL_SPI_LOAD
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if (dev_type == QSPI_DEV) {
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struct spi_flash *flash = (struct spi_flash *)dev;
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ret = spi_flash_read(flash, offset,
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CONTAINER_HDR_ALIGNMENT, buf);
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if (ret != 0) {
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printf("Read container image from QSPI failed\n");
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return -EIO;
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}
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}
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#endif
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#ifdef CONFIG_SPL_NAND_SUPPORT
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if (dev_type == NAND_DEV) {
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ret = nand_spl_load_image(offset, CONTAINER_HDR_ALIGNMENT,
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buf);
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if (ret != 0) {
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printf("Read container image from NAND failed\n");
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return -EIO;
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}
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}
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#endif
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#ifdef CONFIG_SPL_NOR_SUPPORT
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if (dev_type == QSPI_NOR_DEV)
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memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT);
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#endif
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ret = __get_container_size((ulong)buf);
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free(buf);
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return ret;
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}
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static unsigned long get_boot_device_offset(void *dev, int dev_type)
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{
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unsigned long offset = 0;
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if (dev_type == MMC_DEV) {
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struct mmc *mmc = (struct mmc *)dev;
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if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
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offset = CONTAINER_HDR_MMCSD_OFFSET;
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} else {
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u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
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if (part == 1 || part == 2) {
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if (is_imx8qxp() && is_soc_rev(CHIP_REV_B))
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offset = CONTAINER_HDR_MMCSD_OFFSET;
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else
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offset = CONTAINER_HDR_EMMC_OFFSET;
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} else {
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offset = CONTAINER_HDR_MMCSD_OFFSET;
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}
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}
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} else if (dev_type == QSPI_DEV) {
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offset = CONTAINER_HDR_QSPI_OFFSET;
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} else if (dev_type == NAND_DEV) {
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offset = CONTAINER_HDR_NAND_OFFSET;
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} else if (dev_type == QSPI_NOR_DEV) {
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offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000;
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}
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return offset;
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}
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static int get_imageset_end(void *dev, int dev_type)
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{
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unsigned long offset1 = 0, offset2 = 0;
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int value_container[2];
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offset1 = get_boot_device_offset(dev, dev_type);
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offset2 = CONTAINER_HDR_ALIGNMENT + offset1;
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value_container[0] = get_container_size(dev, dev_type, offset1);
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if (value_container[0] < 0) {
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printf("Parse seco container failed %d\n", value_container[0]);
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return value_container[0];
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}
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debug("seco container size 0x%x\n", value_container[0]);
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value_container[1] = get_container_size(dev, dev_type, offset2);
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if (value_container[1] < 0) {
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debug("Parse scu container failed %d, only seco container\n",
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value_container[1]);
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/* return seco container total size */
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return value_container[0] + offset1;
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}
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debug("scu container size 0x%x\n", value_container[1]);
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return value_container[1] + offset2;
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}
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#ifdef CONFIG_SPL_SPI_LOAD
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unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash)
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{
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int end;
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end = get_imageset_end(flash, QSPI_DEV);
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end = ROUND(end, SZ_1K);
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printf("Load image from QSPI 0x%x\n", end);
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return end;
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}
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#endif
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#ifdef CONFIG_SPL_MMC_SUPPORT
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unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
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unsigned long raw_sect)
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{
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int end;
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end = get_imageset_end(mmc, MMC_DEV);
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end = ROUND(end, SZ_1K);
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printf("Load image from MMC/SD 0x%x\n", end);
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return end / mmc->read_bl_len;
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}
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#endif
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#ifdef CONFIG_SPL_NAND_SUPPORT
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uint32_t spl_nand_get_uboot_raw_page(void)
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{
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int end;
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end = get_imageset_end((void *)NULL, NAND_DEV);
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end = ROUND(end, SZ_16K);
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printf("Load image from NAND 0x%x\n", end);
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return end;
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}
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#endif
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#ifdef CONFIG_SPL_NOR_SUPPORT
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unsigned long spl_nor_get_uboot_base(void)
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{
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int end;
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/* Calculate the image set end,
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* if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000),
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* we use CONFIG_SYS_UBOOT_BASE
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* Otherwise, use the calculated address
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*/
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end = get_imageset_end((void *)NULL, QSPI_NOR_DEV);
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if (end <= CONFIG_SYS_UBOOT_BASE)
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end = CONFIG_SYS_UBOOT_BASE;
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else
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end = ROUND(end, SZ_1K);
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printf("Load image from NOR 0x%x\n", end);
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return end;
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}
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#endif
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