mirror of
https://github.com/AsahiLinux/u-boot
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3a187cff7a
LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
255 lines
6.3 KiB
C
255 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014-2015, Freescale Semiconductor, Inc.
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* Copyright 2019-2020 NXP
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*
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* Derived from arch/power/cpu/mpc85xx/speed.c
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <cpu_func.h>
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#include <linux/compiler.h>
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#include <fsl_ifc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/arch-fsl-layerscape/immap_lsch3.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/soc.h>
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#include "cpu.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
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#endif
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void get_sys_info(struct sys_info *sys_info)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
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(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
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(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
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};
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struct ccsr_clk_ctrl __iomem *clk_ctrl =
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(void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
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unsigned int cpu;
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const u8 core_cplx_pll[16] = {
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[0] = 0, /* CC1 PPL / 1 */
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[1] = 0, /* CC1 PPL / 2 */
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[2] = 0, /* CC1 PPL / 4 */
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[4] = 1, /* CC2 PPL / 1 */
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[5] = 1, /* CC2 PPL / 2 */
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[6] = 1, /* CC2 PPL / 4 */
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[8] = 2, /* CC3 PPL / 1 */
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[9] = 2, /* CC3 PPL / 2 */
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[10] = 2, /* CC3 PPL / 4 */
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[12] = 3, /* CC4 PPL / 1 */
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[13] = 3, /* CC4 PPL / 2 */
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[14] = 3, /* CC4 PPL / 4 */
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};
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const u8 core_cplx_pll_div[16] = {
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[0] = 1, /* CC1 PPL / 1 */
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[1] = 2, /* CC1 PPL / 2 */
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[2] = 4, /* CC1 PPL / 4 */
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[4] = 1, /* CC2 PPL / 1 */
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[5] = 2, /* CC2 PPL / 2 */
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[6] = 4, /* CC2 PPL / 4 */
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[8] = 1, /* CC3 PPL / 1 */
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[9] = 2, /* CC3 PPL / 2 */
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[10] = 4, /* CC3 PPL / 4 */
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[12] = 1, /* CC4 PPL / 1 */
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[13] = 2, /* CC4 PPL / 2 */
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[14] = 4, /* CC4 PPL / 4 */
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};
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uint i, cluster;
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#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
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uint rcw_tmp;
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#endif
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uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
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uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
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u32 c_pll_sel, cplx_pll;
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void *offset;
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sys_info->freq_systembus = sysclk;
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#ifdef CONFIG_DDR_CLK_FREQ
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sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
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#endif
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#else
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sys_info->freq_ddrbus = sysclk;
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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sys_info->freq_ddrbus2 = sysclk;
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#endif
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#endif
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/* The freq_systembus is used to record frequency of platform PLL */
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sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
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sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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if (soc_has_dp_ddr()) {
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sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
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FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
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FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
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} else {
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sys_info->freq_ddrbus2 = 0;
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}
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#endif
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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/*
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* fixme: prefer to combine the following into one line, but
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* cannot pass compiling without warning about in_le32.
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*/
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offset = (void *)((size_t)clk_grp[i/3] +
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offsetof(struct ccsr_clk_cluster_group,
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pllngsr[i%3].gsr));
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ratio[i] = (in_le32(offset) >> 1) & 0x3f;
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freq_c_pll[i] = sysclk * ratio[i];
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}
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for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
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cluster = fsl_qoriq_core_to_cluster(cpu);
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c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
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& 0xf;
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cplx_pll = core_cplx_pll[c_pll_sel];
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cplx_pll += cc_group[cluster] - 1;
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sys_info->freq_processor[cpu] =
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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#if defined(CONFIG_FSL_IFC)
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sys_info->freq_localbus = sys_info->freq_systembus /
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CONFIG_SYS_FSL_IFC_CLK_DIV;
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#endif
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#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
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#define HWA_CGA_M2_CLK_SEL 0x00380000
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#define HWA_CGA_M2_CLK_SHIFT 19
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rcw_tmp = in_le32(&gur->rcwsr[5]);
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switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
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case 1:
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sys_info->freq_cga_m2 = freq_c_pll[1];
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break;
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case 2:
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sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
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break;
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case 3:
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sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
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break;
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case 4:
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sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
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break;
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case 6:
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sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
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break;
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case 7:
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sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
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break;
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default:
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printf("Error: Unknown peripheral clock select!\n");
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break;
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}
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#endif
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}
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int get_clocks(void)
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{
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struct sys_info sys_info;
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#ifdef CONFIG_FSL_ESDHC
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u32 clock = 0;
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#endif
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get_sys_info(&sys_info);
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gd->cpu_clk = sys_info.freq_processor[0];
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gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
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gd->mem_clk = sys_info.freq_ddrbus;
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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gd->arch.mem2_clk = sys_info.freq_ddrbus2;
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#endif
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#ifdef CONFIG_FSL_ESDHC
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#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
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clock = sys_info.freq_cga_m2;
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#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
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clock = sys_info.freq_systembus;
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#endif
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gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
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gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
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#endif
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if (gd->cpu_clk != 0)
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return 0;
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else
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return 1;
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}
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/********************************************
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* get_bus_freq
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* return platform clock in Hz
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*********************************************/
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ulong get_bus_freq(ulong dummy)
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{
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if (!gd->bus_clk)
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get_clocks();
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return gd->bus_clk;
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}
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/********************************************
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* get_ddr_freq
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* return ddr bus freq in Hz
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*********************************************/
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ulong get_ddr_freq(ulong ctrl_num)
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{
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if (!gd->mem_clk)
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get_clocks();
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/*
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* DDR controller 0 & 1 are on memory complex 0
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* DDR controller 2 is on memory complext 1
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*/
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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if (ctrl_num >= 2)
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return gd->arch.mem2_clk;
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#endif
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return gd->mem_clk;
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}
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int get_i2c_freq(ulong dummy)
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{
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return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
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}
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int get_dspi_freq(ulong dummy)
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{
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return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
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}
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int get_serial_clock(void)
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{
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return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_I2C_CLK:
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return get_i2c_freq(0);
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case MXC_DSPI_CLK:
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return get_dspi_freq(0);
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default:
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printf("Unsupported clock\n");
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}
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return 0;
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}
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