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9e0081d573
The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0 register is actually composed of two bit-fields: one pre-divider and one post-divider. This patch fixes the CCM access macros and the code using them accordingly. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
103 lines
2.6 KiB
ArmAsm
103 lines
2.6 KiB
ArmAsm
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/imx-regs.h>
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.macro REG reg, val
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ldr r2, =\reg
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ldr r3, =\val
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str r3, [r2]
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.endm
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.macro REG8 reg, val
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ldr r2, =\reg
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ldr r3, =\val
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strb r3, [r2]
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.endm
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.macro DELAY loops
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ldr r2, =\loops
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1:
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subs r2, r2, #1
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nop
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bcs 1b
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.endm
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.globl lowlevel_init
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lowlevel_init:
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REG IPU_CONF, IPU_CONF_DI_EN
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REG CCM_CCMR, 0x074B0BF5
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DELAY 0x40000
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REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
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REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
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REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
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REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
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REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
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REG 0x43FAC26C, 0 /* SDCLK */
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REG 0x43FAC270, 0 /* CAS */
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REG 0x43FAC274, 0 /* RAS */
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REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */
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REG 0x43FAC284, 0 /* DQM3 */
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REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
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REG 0x43FAC28C, 0
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REG 0x43FAC290, 0
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REG 0x43FAC294, 0
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REG 0x43FAC298, 0
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REG 0x43FAC29C, 0
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REG 0x43FAC2A0, 0
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REG 0x43FAC2A4, 0
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REG 0x43FAC2A8, 0
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REG 0x43FAC2AC, 0
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REG 0x43FAC2B0, 0
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REG 0x43FAC2B4, 0
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REG 0x43FAC2B8, 0
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REG 0x43FAC2BC, 0
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REG 0x43FAC2C0, 0
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REG 0x43FAC2C4, 0
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REG 0x43FAC2C8, 0
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REG 0x43FAC2CC, 0
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REG 0x43FAC2D0, 0
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REG 0x43FAC2D4, 0
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REG 0x43FAC2D8, 0
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REG 0x43FAC2DC, 0
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REG 0xB8001010, 0x00000004
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REG 0xB8001004, 0x006ac73a
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REG 0xB8001000, 0x92100000
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REG 0x80000f00, 0x12344321
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REG 0xB8001000, 0xa2100000
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REG 0x80000000, 0x12344321
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REG 0x80000000, 0x12344321
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REG 0xB8001000, 0xb2100000
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REG8 0x80000033, 0xda
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REG8 0x81000000, 0xff
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REG 0xB8001000, 0x82226080
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REG 0x80000000, 0xDEADBEEF
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REG 0xB8001010, 0x0000000c
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mov pc, lr
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