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https://github.com/AsahiLinux/u-boot
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c35f8e5017
These board files have inconsistent #include ordering. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
154 lines
3.8 KiB
C
154 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <ram.h>
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#include <spl.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3368.h>
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#include <asm/arch/grf_rk3368.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/timer.h>
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/*
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* The SPL (and also the full U-Boot stage on the RK3368) will run in
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* secure mode (i.e. EL3) and an ATF will eventually be booted before
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* starting up the operating system... so we can initialize the SGRF
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* here and rely on the ATF installing the final (secure) policy
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* later.
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*/
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static inline uintptr_t sgrf_soc_con_addr(unsigned no)
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{
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const uintptr_t SGRF_BASE =
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(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
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return SGRF_BASE + sizeof(u32) * no;
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}
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static inline uintptr_t sgrf_busdmac_addr(unsigned no)
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{
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const uintptr_t SGRF_BASE =
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(uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
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const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
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const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
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return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
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}
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static void sgrf_init(void)
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{
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struct rk3368_cru * const cru =
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(struct rk3368_cru * const)rockchip_get_cru();
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const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
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const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
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const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
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/* Set all configurable IP to 'non secure'-mode */
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rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
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rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
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rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
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/*
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* From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
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* Original comment: "ddr space set no secure mode"
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*/
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rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
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rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
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rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
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/* Set 'secure dma' to 'non secure'-mode */
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rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
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rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
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dsb(); /* barrier */
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rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
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rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
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dsb(); /* barrier */
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udelay(10);
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rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
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rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
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}
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void board_debug_uart_init(void)
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{
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/*
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* N.B.: This is called before the device-model has been
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* initialised. For this reason, we can not access
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* the GRF address range using the syscon API.
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*/
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struct rk3368_grf * const grf =
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(struct rk3368_grf * const)0xff770000;
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enum {
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GPIO2D1_MASK = GENMASK(3, 2),
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GPIO2D1_GPIO = 0,
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GPIO2D1_UART0_SOUT = (1 << 2),
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GPIO2D0_MASK = GENMASK(1, 0),
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GPIO2D0_GPIO = 0,
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GPIO2D0_UART0_SIN = (1 << 0),
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};
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
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/* Enable early UART0 on the RK3368 */
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rk_clrsetreg(&grf->gpio2d_iomux,
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GPIO2D0_MASK, GPIO2D0_UART0_SIN);
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rk_clrsetreg(&grf->gpio2d_iomux,
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GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
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#endif
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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#define EARLY_UART
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#ifdef EARLY_UART
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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debug_uart_init();
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printascii("U-Boot TPL board init\n");
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#endif
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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/* Reset security, so we can use DMA in the MMC drivers */
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sgrf_init();
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return;
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}
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}
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void board_return_to_bootrom(void)
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{
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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