mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 10:52:09 +00:00
8c103c33fb
Now that Linux has accepted these tags, move the device tree files in U-Boot over to use them. Signed-off-by: Simon Glass <sjg@chromium.org>
137 lines
1.7 KiB
Text
137 lines
1.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include "imx8mm-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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&aips4 {
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bootph-pre-ram;
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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};
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&pinctrl_reg_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_gpio {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&uart2 {
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bootph-pre-ram;
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};
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&usbmisc1 {
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bootph-pre-ram;
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};
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&usbphynop1 {
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bootph-pre-ram;
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};
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&usbotg1 {
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bootph-pre-ram;
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};
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&usdhc1 {
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bootph-pre-ram;
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};
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&usdhc2 {
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bootph-pre-ram;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
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};
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&usdhc3 {
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bootph-pre-ram;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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/*
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* prevents voltage switch warn: driver will switch even at
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* fixed voltage
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*/
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/delete-property/ vmmc-supply;
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/delete-property/ vqmmc-supply;
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assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
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};
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&i2c1 {
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bootph-pre-ram;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
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bootph-pre-ram;
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};
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&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
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bootph-pre-ram;
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};
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&pinctrl_i2c1 {
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bootph-pre-ram;
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};
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&pinctrl_pmic {
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bootph-pre-ram;
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};
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&wdog1 {
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bootph-pre-ram;
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};
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