Stefano Babic c4559daa91 MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged ... After an update to the MX51 reference manual (Rev. 5), the values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH are now clearly wrong: "Bit 13: High / Low Output Voltage Range. This bit selects the output voltage mode for SD2_CMD. 0 High output voltage mode 1 Low output voltage mode" The values are currently negated in code - fixed. Reported-by: David Jander <david.jander@protonic.nl> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marek.vasut@gmail.com> CC: David Jander <david.jander@protonic.nl> Acked-by: David Jander <david.jander@protonic.nl> Acked-by: Marek Vasut <marek.vasut@gmail.com>		2012-05-15 08:31:35 +02:00
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cpu	i.MX28: Add delay after CPU bypass is cleared	2012-05-15 08:31:35 +02:00
dts	tegra: fdt: i2c: Add extra I2C bindings for U-Boot	2012-03-29 08:12:50 +02:00
include/asm	MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged	2012-05-15 08:31:35 +02:00
lib	arm: restore fdt_fixup_ethernet call to do_bootm_linux	2012-04-23 22:11:18 +02:00
config.mk	Makefile: Add a 'checkthumb' rule	2012-05-15 08:31:26 +02:00