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https://github.com/AsahiLinux/u-boot
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bf637ea5e4
Many options are duplicated on the exynos5 boards. Move these to the common files. Also some options are not used so can be removed. Tidy this up to make the files easier to maintain. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
231 lines
6.2 KiB
C
231 lines
6.2 KiB
C
/*
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* Copyright (C) 2013 Samsung Electronics
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*
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* Configuration settings for the SAMSUNG EXYNOS5 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_EXYNOS5_COMMON_H
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#define __CONFIG_EXYNOS5_COMMON_H
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#define CONFIG_EXYNOS5 /* Exynos5 Family */
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#include "exynos-common.h"
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_EXYNOS_SPL
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#ifdef FTRACE
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#define CONFIG_TRACE
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#define CONFIG_CMD_TRACE
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#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
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#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
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#define CONFIG_TRACE_EARLY
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#define CONFIG_TRACE_EARLY_ADDR 0x50000000
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#endif
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/* Enable ACE acceleration for SHA1 and SHA256 */
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#define CONFIG_EXYNOS_ACE_SHA
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#define CONFIG_SHA_HW_ACCEL
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/* Power Down Modes */
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#define S5P_CHECK_SLEEP 0x00000BAD
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#define S5P_CHECK_DIDLE 0xBAD00000
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#define S5P_CHECK_LPA 0xABAD0000
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/* Offset for inform registers */
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#define INFORM0_OFFSET 0x800
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#define INFORM1_OFFSET 0x804
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#define INFORM2_OFFSET 0x808
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#define INFORM3_OFFSET 0x80c
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/* select serial console configuration */
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#define CONFIG_BAUDRATE 115200
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#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
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#define CONFIG_SILENT_CONSOLE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_CMD_HASH
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/* Thermal Management Unit */
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#define CONFIG_EXYNOS_TMU
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#define CONFIG_CMD_DTT
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#define CONFIG_TMU_CMD_DTT
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/* TPM */
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#define CONFIG_TPM
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#define CONFIG_CMD_TPM
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#define CONFIG_TPM_TIS_I2C
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#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
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#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
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/* MMC SPL */
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#define COPY_BL2_FNPTR_ADDR 0x02020030
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#define CONFIG_SUPPORT_EMMC_BOOT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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/* specific .lds file */
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#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
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/* Boot Argument Buffer Size */
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
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#define CONFIG_RD_LVL
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
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#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
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#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
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#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
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#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SECURE_BL1_ONLY
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/* Secure FW size configuration */
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#ifdef CONFIG_SECURE_BL1_ONLY
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#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
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#else
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#define CONFIG_SEC_FW_SIZE 0
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#endif
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/* Configuration of BL1, BL2, ENV Blocks on mmc */
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#define CONFIG_RES_BLOCK_SIZE (512)
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#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
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#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
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#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
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#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
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/* U-boot copy size from boot Media to DRAM.*/
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#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
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#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
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#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
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#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
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/* I2C */
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C_S3C24X0
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#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
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#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
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#define CONFIG_I2C_EDID
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/* SPI */
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#ifdef CONFIG_SPI_FLASH
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#define CONFIG_EXYNOS_SPI
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SPI_FLASH_GIGADEVICE
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 50000000
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#endif
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#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
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#define CONFIG_ENV_SPI_BUS 1
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#define CONFIG_ENV_SPI_MAX_HZ 50000000
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#endif
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/* Ethernet Controllor Driver */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_BASE 0x5000000
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#define CONFIG_SMC911X_16_BIT
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#define CONFIG_ENV_SROM_BANK 1
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#endif /*CONFIG_CMD_NET*/
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/* SHA hashing */
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#define CONFIG_CMD_HASH
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#define CONFIG_HASH_VERIFY
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#define CONFIG_SHA1
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#define CONFIG_SHA256
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/* Enable Time Command */
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#define CONFIG_CMD_TIME
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#define CONFIG_CMD_GPIO
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/* USB */
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#define CONFIG_CMD_USB
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_XHCI_DWC3
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_USB_ETHER_SMSC95XX
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/* USB boot mode */
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#define CONFIG_USB_BOOTING
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#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
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#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
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#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
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/* Enable FIT support and comparison */
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#define CONFIG_FIT
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#define CONFIG_FIT_BEST_MATCH
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(PXE, pxe, na) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#ifndef MEM_LAYOUT_ENV_SETTINGS
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/* 2GB RAM, bootm size of 256M, load scripts after that */
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"kernel_addr_r=0x42000000\0" \
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"fdt_addr_r=0x43000000\0" \
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"ramdisk_addr_r=0x43300000\0" \
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"scriptaddr=0x50000000\0" \
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"pxefile_addr_r=0x51000000\0"
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#endif
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#ifndef EXYNOS_DEVICE_SETTINGS
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#define EXYNOS_DEVICE_SETTINGS \
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"stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0"
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#endif
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#ifndef EXYNOS_FDTFILE_SETTING
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#define EXYNOS_FDTFILE_SETTING
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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EXYNOS_DEVICE_SETTINGS \
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EXYNOS_FDTFILE_SETTING \
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MEM_LAYOUT_ENV_SETTINGS \
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BOOTENV
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#endif /* __CONFIG_EXYNOS5_COMMON_H */
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