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ff9112df8b
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP (AXP) devices (and perhaps Armada 370)
drivers/ddr/marvell/a38x
Supporting Armada 38x devices (and perhaps Armada 39x)
Signed-off-by: Stefan Roese <sr@denx.de>
144 lines
4.2 KiB
C
144 lines
4.2 KiB
C
/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_DB_MV7846MP_GP_H
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#define _CONFIG_DB_MV7846MP_GP_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_ARMADA_XP /* SOC Family Name */
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#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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#define CONFIG_SYS_TEXT_BASE 0x04000000
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/*
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* Commands configuration
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*/
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#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_TFTPPUT
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#define CONFIG_CMD_TIME
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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/* SPI NOR flash default params, used by sf commands */
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#define CONFIG_SF_DEFAULT_SPEED 1000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
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#define CONFIG_SPI_FLASH_STMICRO
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/* Environment in SPI NOR flash */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
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#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
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#define CONFIG_PHY_MARVELL /* there is a marvell phy */
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#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
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#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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#define CONFIG_RESET_PHY_R
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
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#define CONFIG_SYS_ALT_MEMTEST
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/* SATA support */
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#ifdef CONFIG_CMD_IDE
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#define __io
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#define CONFIG_IDE_PREINIT
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#define CONFIG_MVSATA_IDE
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/* Needs byte-swapping for ATA data register */
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#define CONFIG_IDE_SWAP_IO
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#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */
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#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
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/* Each 8-bit ATA register is aligned to a 4-bytes address */
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#define CONFIG_SYS_ATA_STRIDE 4
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/* CONFIG_CMD_IDE requires some #defines for ATA registers */
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#define CONFIG_SYS_IDE_MAXBUS 2
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#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS
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/* ATA registers base is at SATA controller base */
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#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
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#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
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#define CONFIG_DOS_PARTITION
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#endif /* CONFIG_CMD_IDE */
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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/*
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* Memory layout while starting into the bin_hdr via the
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* BootROM:
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*
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* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
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* 0x4000.4030 bin_hdr start address
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* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
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* 0x4007.fffc BootROM stack top
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*
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* The address space between 0x4007.fffc and 0x400f.fff is not locked in
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* L2 cache thus cannot be used.
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*/
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x40004030
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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/* SPL related SPI defines */
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_MVEBU_DDR_AXP
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#define CONFIG_SPD_EEPROM 0x4e
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#endif /* _CONFIG_DB_MV7846MP_GP_H */
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