mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 11:18:28 +00:00
09f3ca3dd5
We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
355 lines
13 KiB
C
355 lines
13 KiB
C
/*
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* (C) Copyright 2009
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_405EP 1 /* This is a PPC405 CPU */
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#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
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#undef CONFIG_BOOTARGS
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
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#define CONFIG_HAS_ETH1
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
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#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_CHIP_CONFIG
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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#define CONFIG_PRAM 0
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
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#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
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#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
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#define CONFIG_CONS_INDEX 2 /* Use UART1 */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK
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#define CONFIG_SYS_BASE_BAUD 691200
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*
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* PCI stuff
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*/
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#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
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#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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/*
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* PCI identification
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*/
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
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#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
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#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
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#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
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#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
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#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
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#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
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#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
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#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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/*
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* FLASH organization
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*/
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#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
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#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xfe000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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/*
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* Environment in EEPROM setup
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*/
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#define CONFIG_ENV_IS_IN_EEPROM 1
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#define CONFIG_ENV_OFFSET 0x100
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#define CONFIG_ENV_SIZE 0x700
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/*
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* I2C EEPROM (24W16) for environment
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_PPC4XX
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#define CONFIG_SYS_I2C_PPC4XX_CH0
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
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#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CONFIG_SYS_EEPROM_WREN 1
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
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#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
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#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
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/*
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* RTC
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*/
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#define CONFIG_RTC_RX8025
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/*
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* External Bus Controller (EBC) Setup
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* (max. 55MHZ EBC clock)
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*/
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/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
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#define CONFIG_SYS_EBC_PB0AP 0x03017200
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#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
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/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
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#define CONFIG_SYS_CPLD_BASE 0xef000000
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#define CONFIG_SYS_EBC_PB1AP 0x00800000
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#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
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/*
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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/* inside SDRAM */
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
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/* End of used area in RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* GPIO Configuration
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*/
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#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
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{ \
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/* GPIO Core 0 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
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} \
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}
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#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
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#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
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#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
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#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
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#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
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#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
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#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
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#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
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#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
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#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
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/*
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* Default speed selection (cpu_plb_opb_ebc) in mhz.
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* This value will be set if iic boot eprom is disabled.
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*/
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#undef CONFIG_SYS_FCPU333MHZ
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#define CONFIG_SYS_FCPU266MHZ
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#undef CONFIG_SYS_FCPU133MHZ
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#if defined(CONFIG_SYS_FCPU333MHZ)
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/*
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* CPU: 333MHz
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* PLB/SDRAM/MAL: 111MHz
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* OPB: 55MHz
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* EBC: 55MHz
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* PCI: 55MHz (111MHz on M66EN=1)
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*/
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#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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PLL_MALDIV_1 | PLL_PCIDIV_2)
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#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
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#endif
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#if defined(CONFIG_SYS_FCPU266MHZ)
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/*
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* CPU: 266MHz
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* PLB/SDRAM/MAL: 133MHz
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* OPB: 66MHz
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* EBC: 44MHz
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* PCI: 44MHz (66MHz on M66EN=1)
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*/
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#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
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PLL_MALDIV_1 | PLL_PCIDIV_3)
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#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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#endif
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#if defined(CONFIG_SYS_FCPU133MHZ)
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/*
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* CPU: 133MHz
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* PLB/SDRAM/MAL: 133MHz
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* OPB: 66MHz
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* EBC: 44MHz
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* PCI: 44MHz (66MHz on M66EN=1)
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*/
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#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
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PLL_MALDIV_1 | PLL_PCIDIV_3)
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#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
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PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
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#endif
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#endif /* __CONFIG_H */
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