mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 12:45:42 +00:00
594708dd9d
P1020 integrated 2 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
35 lines
956 B
Text
35 lines
956 B
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* P1020RDB-PC Device Tree Source
|
|
*
|
|
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
|
|
* Copyright 2019 NXP
|
|
*/
|
|
|
|
/include/ "p1020.dtsi"
|
|
|
|
/ {
|
|
model = "fsl,P1020RDB-PC";
|
|
compatible = "fsl,P1020RDB-PC";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&mpic>;
|
|
|
|
soc: soc@ffe00000 {
|
|
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
|
};
|
|
|
|
pci1: pcie@ffe09000 {
|
|
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pci0: pcie@ffe0a000 {
|
|
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
};
|
|
|
|
/include/ "p1020-post.dtsi"
|