u-boot/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
Marek Vasut c3880e6597 arm: socfpga: vining: Fix UDC controller phandle in DT
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00

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// SPDX-License-Identifier: (GPL-2.0+ OR X11)
/*
* U-Boot additions
*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
* Copyright (c) 2018 Simon Goldschmidt
*/
#include "socfpga-common-u-boot.dtsi"
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb1;
};
};
&mmc {
status = "disabled";
};
&qspi {
u-boot,dm-pre-reloc;
n25q128@0 {
compatible = "n25q128", "jedec,spi-nor";
u-boot,dm-pre-reloc;
};
n25q00@1 {
compatible = "n25q00", "jedec,spi-nor";
u-boot,dm-pre-reloc;
};
};
&uart0 {
clock-frequency = <100000000>;
u-boot,dm-pre-reloc;
};
&uart1 {
clock-frequency = <100000000>;
};
&porta {
bank-name = "porta";
};
&portb {
bank-name = "portb";
};
&portc {
bank-name = "portc";
};
&watchdog0 {
u-boot,dm-pre-reloc;
};