mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
438654c87c
Perform simple renames of: CONFIG_VSC7385_IMAGE to CFG_VSC7385_IMAGE CONFIG_VSC7385_IMAGE_SIZE to CFG_VSC7385_IMAGE_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
434 lines
12 KiB
C
434 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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*/
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/*
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* QorIQ RDB boards configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <linux/stringify.h>
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#if defined(CONFIG_TARGET_P1020RDB_PC)
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#define CFG_SLIC
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0x5c
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#define __SW_BOOT_SPI 0x1c
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#define __SW_BOOT_SD 0x9c
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#define __SW_BOOT_NAND 0xec
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#define __SW_BOOT_PCIE 0x6c
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#define __SW_NOR_BANK_MASK 0xfd
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#define __SW_NOR_BANK_UP 0x00
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#define __SW_NOR_BANK_LO 0x02
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#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
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#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
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#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
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#endif
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/*
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* P1020RDB-PD board has user selectable switches for evaluating different
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* frequency and boot options for the P1020 device. The table that
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* follow describe the available options. The front six binary number was in
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* accordance with SW3[1:6].
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* 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
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* 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
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* 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
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* 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
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* 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
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* 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
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* 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
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*/
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CFG_SLIC
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0x64
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#define __SW_BOOT_SPI 0x34
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#define __SW_BOOT_SD 0x24
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#define __SW_BOOT_NAND 0x44
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#define __SW_BOOT_PCIE 0x74
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#define __SW_NOR_BANK_MASK 0xfd
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#define __SW_NOR_BANK_UP 0x00
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#define __SW_NOR_BANK_LO 0x02
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#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
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#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
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#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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#endif
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#if defined(CONFIG_TARGET_P2020RDB)
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#define __SW_BOOT_MASK 0x03
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#define __SW_BOOT_NOR 0xc8
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#define __SW_BOOT_SPI 0x28
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#define __SW_BOOT_SD 0x68
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#define __SW_BOOT_SD2 0x18
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#define __SW_BOOT_NAND 0xe8
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#define __SW_BOOT_PCIE 0xa8
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#define __SW_NOR_BANK_MASK 0xfd
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#define __SW_NOR_BANK_UP 0x00
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#define __SW_NOR_BANK_LO 0x02
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#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
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#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
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#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
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/*
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* Dynamic MTD Partition support with mtdparts
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*/
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#endif
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#ifdef CONFIG_SDCARD
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#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
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#define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
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#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
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#define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
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#else
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#define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
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#endif
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#elif defined(CONFIG_SPIFLASH)
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#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
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#define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE
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#define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE
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#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
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#elif defined(CONFIG_MTD_RAW_NAND)
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#ifdef CONFIG_TPL_BUILD
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#define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10)
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#define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
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#define CFG_SYS_NAND_U_BOOT_START (0x11000000)
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#elif defined(CONFIG_SPL_BUILD)
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#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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#define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000
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#define CFG_SYS_NAND_U_BOOT_START 0xf8f80000
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#endif /* not CONFIG_TPL_BUILD */
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#endif
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#ifndef CFG_RESET_VECTOR_ADDRESS
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#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CFG_SYS_CCSRBAR 0xffe00000
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#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
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/* DDR Setup */
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#define SPD_EEPROM_ADDRESS 0x52
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
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#else
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#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
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#endif
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#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19))
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#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
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/* Default settings for DDR3 */
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#ifndef CONFIG_TARGET_P2020RDB
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#define CFG_SYS_DDR_CS0_BNDS 0x0000003f
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#define CFG_SYS_DDR_CS0_CONFIG 0x80014302
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#define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CFG_SYS_DDR_CS1_BNDS 0x0040007f
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#define CFG_SYS_DDR_CS1_CONFIG 0x80014302
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#define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000
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#define CFG_SYS_DDR_INIT_ADDR 0x00000000
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#define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CFG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CFG_SYS_DDR_ZQ_CONTROL 0x89080600
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#define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608
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#define CFG_SYS_DDR_SR_CNTR 0x00000000
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#define CFG_SYS_DDR_RCW_1 0x00000000
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#define CFG_SYS_DDR_RCW_2 0x00000000
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#define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
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#define CFG_SYS_DDR_CONTROL_2 0x04401050
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#define CFG_SYS_DDR_TIMING_4 0x00220001
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#define CFG_SYS_DDR_TIMING_5 0x03402400
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#define CFG_SYS_DDR_TIMING_3 0x00020000
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#define CFG_SYS_DDR_TIMING_0 0x00330004
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#define CFG_SYS_DDR_TIMING_1 0x6f6B4846
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#define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF
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#define CFG_SYS_DDR_CLK_CTRL 0x03000000
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#define CFG_SYS_DDR_MODE_1 0x40461520
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#define CFG_SYS_DDR_MODE_2 0x8000c000
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#define CFG_SYS_DDR_INTERVAL 0x0C300000
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#endif
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
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* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
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* 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
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* 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
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* (early boot only)
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* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
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* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
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* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
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* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CFG_SYS_FLASH_BASE 0xec000000
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#else
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#define CFG_SYS_FLASH_BASE 0xef000000
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#endif
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
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#else
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#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
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#endif
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#define CFG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \
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| BR_PS_16 | BR_V)
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#define CFG_FLASH_OR_PRELIM 0xfc000ff7
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#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
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/* Nand Flash */
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#ifdef CONFIG_NAND_FSL_ELBC
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#define CFG_SYS_NAND_BASE 0xff800000
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
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#else
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#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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#endif
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#if defined(CONFIG_TARGET_P1020RDB_PD)
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#define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
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| OR_FCM_PGS /* Large Page*/ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#else
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#define CFG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#endif
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#endif /* CONFIG_NAND_FSL_ELBC */
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#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
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/* The assembler doesn't like typecast */
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#define CFG_SYS_INIT_RAM_ADDR_PHYS \
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((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#else
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/* Initial L1 address */
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#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
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#endif
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/* Size of used area in RAM */
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#define CFG_SYS_INIT_RAM_SIZE 0x00004000
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#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CFG_SYS_CPLD_BASE 0xffa00000
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
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#else
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#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
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#endif
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/* CPLD config size: 1Mb */
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/* Vsc7385 switch */
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#ifdef CONFIG_VSC7385_ENET
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#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
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#define CFG_SYS_VSC7385_BASE 0xffb00000
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
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#else
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#define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE
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#endif
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/* The size of the VSC7385 firmware image */
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#define CFG_VSC7385_IMAGE_SIZE 8192
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#endif
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#ifndef __VSCFW_ADDR
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#define __VSCFW_ADDR ""
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#endif
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/*
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* Config the L2 Cache as L2 SRAM
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*/
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#if defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
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#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
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#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#elif defined(CONFIG_MTD_RAW_NAND)
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#ifdef CONFIG_TPL_BUILD
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#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
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#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#else
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#define CFG_SYS_INIT_L2_ADDR 0xf8f80000
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#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
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#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
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#endif /* CONFIG_TPL_BUILD */
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#endif
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#endif
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CFG_SYS_NS16550_CLK get_bus_freq(0)
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#define CFG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
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#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
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/* I2C */
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#if !CONFIG_IS_ENABLED(DM_I2C)
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#define CFG_SYS_I2C_NOPROBES { {0, 0x29} }
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#endif
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/*
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* I2C2 EEPROM
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*/
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#define CFG_SYS_I2C_RTC_ADDR 0x68
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#define CFG_SYS_I2C_PCA9557_ADDR 0x18
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/* enable read and write access to EEPROM */
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#if defined(CONFIG_PCI)
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 2, direct to uli, tgtid 2, Base address 9000 */
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#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#else
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#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#endif
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#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
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#else
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#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000
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#endif
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/* controller 1, Slot 2, tgtid 1, Base address a000 */
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#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#else
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#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000
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#endif
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#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000
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#ifdef CONFIG_PHYS_64BIT
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#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
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#else
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#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000
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#endif
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#endif /* CONFIG_PCI */
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/*
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* Environment
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*/
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#if defined(CONFIG_MTD_RAW_NAND)
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#ifdef CONFIG_TPL_BUILD
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#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
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#endif
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#endif
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/*
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* USB
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*/
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#ifdef CONFIG_MMC
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#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
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#endif
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/*
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* Miscellaneous configurable options
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*/
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
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/*
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* Environment Configuration
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*/
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#include "p1_p2_bootsrc.h"
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#define CFG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot=" CONFIG_UBOOTPATH "\0" \
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"loadaddr=1000000\0" \
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"bootfile=uImage\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
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"erase " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
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"cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize; " \
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"protect on " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
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"cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize\0" \
|
|
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=2000000\0" \
|
|
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
|
"fdtaddr=1e00000\0" \
|
|
"bdev=sda1\0" \
|
|
"jffs2nor=mtdblock3\0" \
|
|
"norbootaddr=ef080000\0" \
|
|
"norfdtaddr=ef040000\0" \
|
|
"jffs2nand=mtdblock9\0" \
|
|
"nandbootaddr=100000\0" \
|
|
"nandfdtaddr=80000\0" \
|
|
"ramdisk_size=120000\0" \
|
|
__VSCFW_ADDR \
|
|
MAP_NOR_LO_CMD(map_lowernorbank) \
|
|
MAP_NOR_UP_CMD(map_uppernorbank) \
|
|
RST_NOR_CMD(norboot) \
|
|
RST_NOR_LO_CMD(norlowerboot) \
|
|
RST_NOR_UP_CMD(norupperboot) \
|
|
RST_SPI_CMD(spiboot) \
|
|
RST_SD_CMD(sdboot) \
|
|
RST_SD2_CMD(sd2boot) \
|
|
RST_NAND_CMD(nandboot) \
|
|
RST_PCIE_CMD(pciboot) \
|
|
RST_DEF_CMD(defboot) \
|
|
""
|
|
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|
#endif /* __CONFIG_H */
|