mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
68e1747f9c
Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
30 lines
570 B
C
30 lines
570 B
C
/*
|
|
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef _RESET_MANAGER_H_
|
|
#define _RESET_MANAGER_H_
|
|
|
|
void reset_cpu(ulong addr);
|
|
void reset_deassert_peripherals_handoff(void);
|
|
|
|
struct socfpga_reset_manager {
|
|
u32 status;
|
|
u32 ctrl;
|
|
u32 counts;
|
|
u32 padding1;
|
|
u32 mpu_mod_reset;
|
|
u32 per_mod_reset;
|
|
u32 per2_mod_reset;
|
|
u32 brg_mod_reset;
|
|
};
|
|
|
|
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
|
|
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
|
|
#else
|
|
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
|
|
#endif
|
|
|
|
#endif /* _RESET_MANAGER_H_ */
|