u-boot/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
Heiko Schocher 14c0158b18 arm, am335x: add some missing registers and defines for lcd and epwm support
- add missing register defines in struct cm_perpl
  epwmss0clkctrl
  epwmss2clkctrl
  lcdcclkstctrl
- add missing register defines in struct cm_dpll
  clklcdcpixelclk
- add struct pwmss_regs
- add struct pwmss_ecap_regs
- add LCD Controller base LCD_CNTL_BASE
- add PWM0 controller base PWMSS0_BASE

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
2013-08-28 11:44:59 -04:00

68 lines
1.5 KiB
C

/*
* hardware_am33xx.h
*
* AM33xx hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __AM33XX_HARDWARE_AM33XX_H
#define __AM33XX_HARDWARE_AM33XX_H
/* Module base addresses */
/* UART Base Address */
#define UART0_BASE 0x44E09000
/* GPIO Base address */
#define GPIO2_BASE 0x481AC000
/* Watchdog Timer */
#define WDT_BASE 0x44E35000
/* Control Module Base Address */
#define CTRL_BASE 0x44E10000
#define CTRL_DEVICE_BASE 0x44E10600
/* PRCM Base Address */
#define PRCM_BASE 0x44E00000
#define CM_PER 0x44E00000
#define CM_WKUP 0x44E00400
#define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
#define PRM_RSTST (PRM_RSTCTRL + 8)
/* VTP Base address */
#define VTP0_CTRL_ADDR 0x44E10E0C
#define VTP1_CTRL_ADDR 0x48140E10
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x44E12000
#define DDR_PHY_DATA_ADDR 0x44E120C8
#define DDR_PHY_CMD_ADDR2 0x47C0C800
#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
#define DDR_DATA_REGS_NR 2
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A101000
/* RTC base address */
#define RTC_BASE 0x44E3E000
/* OTG */
#define USB0_OTG_BASE 0x47401000
#define USB1_OTG_BASE 0x47401800
/* LCD Controller */
#define LCD_CNTL_BASE 0x4830E000
/* PWMSS */
#define PWMSS0_BASE 0x48300000
#define AM33XX_ECAP0_BASE 0x48300100
#endif /* __AM33XX_HARDWARE_AM33XX_H */