mirror of
https://github.com/AsahiLinux/u-boot
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c8da6513c0
On system with PL DDR which is placed before PS DDR in DT env_get_bootm_size() and env_get_bootm_low() without specifying bootm_low and bootm_size variables are taking by default gd->bd->bi_dram[0].start and gd->bd->bi_dram[0].size. As you see 0 means bank 0 which doesn't need to be PS ddr and even can be memory above 39bit VA which is what U-Boot supports now. That's why setup bootm variables based on ram_base/ram_size setting to make sure that boot images are placed to the same location as U-Boot is placed. This location should be by default location where OS can boot from. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
93 lines
2.1 KiB
C
93 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2019 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <log.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <i2c.h>
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#include <linux/sizes.h>
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#include "board.h"
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int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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{
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int ret = -EINVAL;
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#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
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struct udevice *dev;
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ofnode eeprom;
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eeprom = ofnode_get_chosen_node("xlnx,eeprom");
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if (!ofnode_valid(eeprom))
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return -ENODEV;
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debug("%s: Path to EEPROM %s\n", __func__,
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ofnode_read_chosen_string("xlnx,eeprom"));
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ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
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if (ret)
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return ret;
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ret = dm_i2c_read(dev, CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, ethaddr, 6);
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if (ret)
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debug("%s: I2C EEPROM MAC address read failed\n", __func__);
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else
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debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr);
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#endif
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return ret;
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}
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#if defined(CONFIG_OF_BOARD) || defined(CONFIG_OF_SEPARATE)
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void *board_fdt_blob_setup(void)
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{
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static void *fdt_blob;
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#if !defined(CONFIG_VERSAL_NO_DDR) && !defined(CONFIG_ZYNQMP_NO_DDR)
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fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR;
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if (fdt_magic(fdt_blob) == FDT_MAGIC)
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return fdt_blob;
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debug("DTB is not passed via %p\n", fdt_blob);
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#endif
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#ifdef CONFIG_SPL_BUILD
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/* FDT is at end of BSS unless it is in a different memory region */
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if (IS_ENABLED(CONFIG_SPL_SEPARATE_BSS))
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fdt_blob = (ulong *)&_image_binary_end;
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else
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fdt_blob = (ulong *)&__bss_end;
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#else
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/* FDT is at end of image */
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fdt_blob = (ulong *)&_end;
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#endif
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if (fdt_magic(fdt_blob) == FDT_MAGIC)
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return fdt_blob;
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debug("DTB is also not passed via %p\n", fdt_blob);
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return NULL;
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}
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#endif
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int board_late_init_xilinx(void)
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{
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ulong initrd_hi;
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env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
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initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
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initrd_hi = round_down(initrd_hi, SZ_16M);
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env_set_addr("initrd_high", (void *)initrd_hi);
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env_set_addr("bootm_low", (void *)gd->ram_base);
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env_set_addr("bootm_size", (void *)gd->ram_size);
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return 0;
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}
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