mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 09:27:35 +00:00
bc6bbd6be8
Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
68 lines
2 KiB
C
68 lines
2 KiB
C
/*
|
|
* Copyright 2009 Freescale Semiconductor, Inc.
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/fsl_ifc.h>
|
|
#include <asm/io.h>
|
|
|
|
void cpu_init_f(void)
|
|
{
|
|
#ifdef CONFIG_FSL_LBC
|
|
fsl_lbc_t *lbc = LBC_BASE_ADDR;
|
|
|
|
/*
|
|
* LCRR - Clock Ratio Register - set up local bus timing
|
|
* when needed
|
|
*/
|
|
out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
|
|
|
|
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
|
|
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
|
|
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
|
|
#else
|
|
#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
|
|
#endif
|
|
#endif
|
|
#ifdef CONFIG_FSL_IFC
|
|
#ifndef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
|
|
#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
|
|
set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
|
|
set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
|
|
set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
|
|
#endif
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
|
|
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
|
|
|
|
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
|
|
|
|
/* set MBECCDIS=1, SBECCDIS=1 */
|
|
out_be32(&l2cache->l2errdis,
|
|
(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
|
|
|
|
/* set L2E=1 & L2SRAM=001 */
|
|
out_be32(&l2cache->l2ctl,
|
|
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
|
|
#endif
|
|
}
|