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This patch adds a brief introduction to the RISC-V architecture and the typical boot process used on a variety of RISC-V platforms. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
81 lines
3.2 KiB
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81 lines
3.2 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+
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.. Copyright (C) 2023, Yu Chien Peter Lin <peterlin@andestech.com>
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RISC-V
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======
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Overview
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--------
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This document outlines the U-Boot boot process for the RISC-V architecture.
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RISC-V is an open-source instruction set architecture (ISA) based on the
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principles of reduced instruction set computing (RISC). It has been designed
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to be flexible and customizable, allowing it to be adapted to different use
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cases, from embedded systems to high performance servers.
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Typical Boot Process
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--------------------
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U-Boot can run in either M-mode or S-mode, depending on whether it runs before
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the initialization of the firmware providing SBI (Supervisor Binary Interface).
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The firmware is necessary in the RISC-V boot process as it serves as a SEE
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(Supervisor Execution Environment) to handle exceptions for the S-mode U-Boot
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or Operating System.
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In between the boot phases, the hartid is passed through the a0 register, and
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the start address of the devicetree is passed through the a1 register.
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As a reference, OpenSBI is an SBI implementation that can be used with U-Boot
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in different modes, see the
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`OpenSBI firmware document <https://github.com/riscv-software-src/opensbi/tree/master/docs/firmware>`_
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for more details.
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M-mode U-Boot
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^^^^^^^^^^^^^
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When running in M-mode U-Boot, it will load the payload image (e.g.
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`fw_payload <https://github.com/riscv-software-src/opensbi/blob/master/docs/firmware/fw_payload.md>`_)
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which contains the firmware and the S-mode Operating System; in this case, you
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can use mkimage to package the payload image into an uImage format, and boot it
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using the bootm command.
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The following diagram illustrates the boot process::
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<-----------( M-mode )----------><--( S-mode )-->
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+----------+ +--------------+ +------------+
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| U-Boot |-->| SBI firmware |--->| OS |
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+----------+ +--------------+ +------------+
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To examine the boot process with the QEMU virt machine, you can follow the
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steps in the "Building U-Boot" section of the following document:
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:doc:`../board/emulation/qemu-riscv`.
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S-mode U-Boot
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^^^^^^^^^^^^^
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RISC-V production boot images may include a U-Boot SPL for platform-specific
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initialization. The U-Boot SPL then loads a FIT image (u-boot.itb), which
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contains a firmware (e.g.
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`fw_dynamic <https://github.com/riscv-software-src/opensbi/blob/master/docs/firmware/fw_dynamic.md>`_)
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providing the SBI, as well as a regular U-Boot (or U-Boot proper) running in
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S-mode. Finally, the S-mode Operating
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System is loaded.
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The following diagram illustrates the boot process::
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<-------------( M-mode )----------><----------( S-mode )------->
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+------------+ +--------------+ +----------+ +----------+
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| U-Boot SPL |-->| SBI firmware |--->| U-Boot |-->| OS |
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+------------+ +--------------+ +----------+ +----------+
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To examine the boot process with the QEMU virt machine, you can follow the
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steps in the "Running U-Boot SPL" section of the following document:
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:doc:`../board/emulation/qemu-riscv`.
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Toolchain
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---------
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You can build the
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`RISC-V GNU toolchain <https://github.com/riscv-collab/riscv-gnu-toolchain>`_
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from scratch, or download a pre-built toolchain from the
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`releases page <https://github.com/riscv-collab/riscv-gnu-toolchain/releases>`_.
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