mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 10:30:32 +00:00
6310eb9da7
- add u-boot.hex target in the top level Makefile - add support for the UNSW/NICTA PLEB 2 board (pleb2) - use -mtune=xscale and -march=armv5 options for PXA
154 lines
3.6 KiB
C
154 lines
3.6 KiB
C
/*
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* linux/include/asm-arm/arch-pxa/hardware.h
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Note: This file was taken from linux-2.4.19-rmk4-pxa1
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*
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* - 2003/01/20 implementation specifics activated
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* Robert Schwebel <r.schwebel@pengutronix.de>
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <linux/config.h>
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#include <asm/mach-types.h>
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/*
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* These are statically mapped PCMCIA IO space for designs using it as a
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* generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
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* The actual PCMCIA code is mapping required IO region at run time.
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*/
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#define PCMCIA_IO_0_BASE 0xf6000000
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#define PCMCIA_IO_1_BASE 0xf7000000
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/*
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* We requires absolute addresses.
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*/
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#define PCIO_BASE 0
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/*
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* Workarounds for at least 2 errata so far require this.
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* The mapping is set in mach-pxa/generic.c.
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*/
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#define UNCACHED_PHYS_0 0xff000000
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#define UNCACHED_ADDR UNCACHED_PHYS_0
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/*
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* Intel PXA internal I/O mappings:
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*
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* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
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* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
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* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
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*/
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/* FIXME: Only this does work for u-boot... find out why... [RS] */
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#define UBOOT_REG_FIX 1
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#ifndef UBOOT_REG_FIX
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#ifndef __ASSEMBLY__
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#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
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#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
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/*
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* This __REG() version gives the same results as the one above, except
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* that we are fooling gcc somehow so it generates far better and smaller
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* assembly code for access to contigous registers. It's a shame that gcc
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* doesn't guess this by itself.
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*/
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#include <asm/types.h>
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typedef struct { volatile u32 offset[4096]; } __regbase;
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# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
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# define __REG(x) __REGP(io_p2v(x))
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#endif
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/* Let's kick gcc's ass again... */
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# define __REG2(x,y) \
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( __builtin_constant_p(y) ? (__REG((x) + (y))) \
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: (*(volatile u32 *)((u32)&__REG(x) + (y))) )
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# define __PREG(x) (io_v2p((u32)&(x)))
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#else
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# define __REG(x) io_p2v(x)
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# define __PREG(x) io_v2p(x)
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# undef io_p2v
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# undef __REG
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# ifndef __ASSEMBLY__
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# define io_p2v(PhAdd) (PhAdd)
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# define __REG(x) (*((volatile u32 *)io_p2v(x)))
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# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
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# else
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# define __REG(x) (x)
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# endif
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#endif /* UBOOT_REG_FIX */
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#include "pxa-regs.h"
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#ifndef __ASSEMBLY__
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/*
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* GPIO edge detection for IRQs:
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* IRQs are generated on Falling-Edge, Rising-Edge, or both.
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* This must be called *before* the corresponding IRQ is registered.
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* Use this instead of directly setting GRER/GFER.
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*/
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#define GPIO_FALLING_EDGE 1
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#define GPIO_RISING_EDGE 2
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#define GPIO_BOTH_EDGES 3
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extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
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/*
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* Handy routine to set GPIO alternate functions
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*/
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extern void set_GPIO_mode( int gpio_mode );
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/*
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* return current lclk frequency in units of 10kHz
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*/
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extern unsigned int get_lclk_frequency_10khz(void);
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#endif
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/*
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* Implementation specifics
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*/
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#ifdef CONFIG_ARCH_LUBBOCK
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#include "lubbock.h"
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#endif
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#ifdef CONFIG_ARCH_PXA_IDP
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#include "idp.h"
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#endif
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#ifdef CONFIG_ARCH_PXA_CERF
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#include "cerf.h"
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#endif
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#ifdef CONFIG_ARCH_CSB226
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#include "csb226.h"
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#endif
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#ifdef CONFIG_ARCH_INNOKOM
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#include "innokom.h"
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#endif
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#ifdef CONFIG_ARCH_PLEB
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#include "pleb.h"
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#endif
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#endif /* _ASM_ARCH_HARDWARE_H */
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