mirror of
https://github.com/AsahiLinux/u-boot
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8a33201d0c
Fix: bat_rw.c: In function 'write_bat': bat_rw.c:38:6: warning: variable 'batn' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Andy Fleming <afleming@gmail.com>
261 lines
5.6 KiB
C
261 lines
5.6 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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#ifdef CONFIG_ADDR_MAP
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#include <addr_map.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
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{
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__maybe_unused int batn = -1;
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sync();
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switch (bat) {
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case DBAT0:
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mtspr (DBAT0L, lower);
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mtspr (DBAT0U, upper);
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batn = 0;
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break;
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case IBAT0:
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mtspr (IBAT0L, lower);
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mtspr (IBAT0U, upper);
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break;
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case DBAT1:
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mtspr (DBAT1L, lower);
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mtspr (DBAT1U, upper);
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batn = 1;
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break;
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case IBAT1:
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mtspr (IBAT1L, lower);
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mtspr (IBAT1U, upper);
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break;
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case DBAT2:
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mtspr (DBAT2L, lower);
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mtspr (DBAT2U, upper);
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batn = 2;
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break;
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case IBAT2:
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mtspr (IBAT2L, lower);
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mtspr (IBAT2U, upper);
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break;
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case DBAT3:
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mtspr (DBAT3L, lower);
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mtspr (DBAT3U, upper);
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batn = 3;
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break;
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case IBAT3:
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mtspr (IBAT3L, lower);
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mtspr (IBAT3U, upper);
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break;
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#ifdef CONFIG_HIGH_BATS
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case DBAT4:
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mtspr (DBAT4L, lower);
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mtspr (DBAT4U, upper);
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batn = 4;
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break;
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case IBAT4:
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mtspr (IBAT4L, lower);
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mtspr (IBAT4U, upper);
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break;
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case DBAT5:
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mtspr (DBAT5L, lower);
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mtspr (DBAT5U, upper);
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batn = 5;
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break;
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case IBAT5:
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mtspr (IBAT5L, lower);
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mtspr (IBAT5U, upper);
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break;
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case DBAT6:
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mtspr (DBAT6L, lower);
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mtspr (DBAT6U, upper);
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batn = 6;
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break;
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case IBAT6:
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mtspr (IBAT6L, lower);
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mtspr (IBAT6U, upper);
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break;
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case DBAT7:
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mtspr (DBAT7L, lower);
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mtspr (DBAT7U, upper);
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batn = 7;
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break;
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case IBAT7:
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mtspr (IBAT7L, lower);
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mtspr (IBAT7U, upper);
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break;
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#endif
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default:
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return (-1);
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}
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#ifdef CONFIG_ADDR_MAP
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if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) {
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phys_size_t size;
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if (!BATU_VALID(upper))
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size = 0;
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else
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size = BATU_SIZE(upper);
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addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
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size, batn);
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}
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#endif
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sync();
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isync();
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return (0);
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}
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int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
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{
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unsigned long register u;
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unsigned long register l;
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switch (bat) {
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case DBAT0:
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l = mfspr (DBAT0L);
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u = mfspr (DBAT0U);
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break;
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case IBAT0:
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l = mfspr (IBAT0L);
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u = mfspr (IBAT0U);
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break;
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case DBAT1:
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l = mfspr (DBAT1L);
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u = mfspr (DBAT1U);
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break;
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case IBAT1:
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l = mfspr (IBAT1L);
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u = mfspr (IBAT1U);
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break;
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case DBAT2:
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l = mfspr (DBAT2L);
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u = mfspr (DBAT2U);
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break;
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case IBAT2:
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l = mfspr (IBAT2L);
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u = mfspr (IBAT2U);
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break;
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case DBAT3:
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l = mfspr (DBAT3L);
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u = mfspr (DBAT3U);
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break;
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case IBAT3:
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l = mfspr (IBAT3L);
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u = mfspr (IBAT3U);
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break;
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#ifdef CONFIG_HIGH_BATS
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case DBAT4:
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l = mfspr (DBAT4L);
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u = mfspr (DBAT4U);
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break;
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case IBAT4:
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l = mfspr (IBAT4L);
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u = mfspr (IBAT4U);
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break;
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case DBAT5:
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l = mfspr (DBAT5L);
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u = mfspr (DBAT5U);
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break;
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case IBAT5:
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l = mfspr (IBAT5L);
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u = mfspr (IBAT5U);
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break;
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case DBAT6:
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l = mfspr (DBAT6L);
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u = mfspr (DBAT6U);
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break;
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case IBAT6:
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l = mfspr (IBAT6L);
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u = mfspr (IBAT6U);
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break;
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case DBAT7:
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l = mfspr (DBAT7L);
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u = mfspr (DBAT7U);
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break;
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case IBAT7:
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l = mfspr (IBAT7L);
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u = mfspr (IBAT7U);
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break;
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#endif
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default:
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return (-1);
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}
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*upper = u;
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*lower = l;
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return (0);
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}
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void print_bats(void)
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{
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printf("BAT registers:\n");
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printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L));
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printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U));
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printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L));
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printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U));
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printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L));
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printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U));
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printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L));
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printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U));
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printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L));
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printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U));
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printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L));
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printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U));
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printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L));
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printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U));
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printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L));
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printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U));
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#ifdef CONFIG_HIGH_BATS
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printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L));
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printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U));
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printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L));
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printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U));
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printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L));
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printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U));
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printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L));
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printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U));
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printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L));
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printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U));
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printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L));
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printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U));
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printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L));
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printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U));
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printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L));
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printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U));
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#endif
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}
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