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96b109ba74
Update the driver to support the device tree and the driver model.
Timings and panel parameters are now loaded from the device tree.
The DM code replaces the am335x_lcdpanel structure with
tilcdc_panel_info taken from the linux kernel, as well the management
of additional parameters not covered in the legacy code. In addition,
the am335x_lcdpanel structure contains parameters and operations that
were probably a requirement of the board for which this driver was
developed and which, however, were not developed in the linux kernel.
All this led to rewrite th DM controller initialization code, except
for the pixel clock setting that is executed in a function created in a
previous patch with code taken from the legacy am335xfb_init.
The patch has been tested on a custom board with u-boot 2018.11-rc2 and
the following device-tree configuration:
panel {
compatible = "ti,tilcdc,panel";
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_pins>;
enable-gpios = <&gpio0 31 0>;
backlight = <&backlight>;
status = "okay";
u-boot,dm-pre-reloc;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <16>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: 800x480 {
hactive = <800>;
vactive = <480>;
hback-porch = <46>;
hfront-porch = <210>;
hsync-len = <20>;
vback-porch = <23>;
vfront-porch = <22>;
vsync-len = <10>;
clock-frequency = <33000000>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Tested-by: Dario Binacchi <dariobin@libero.it>
75 lines
2.2 KiB
C
75 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at> -
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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*/
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#ifndef AM335X_FB_H
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#define AM335X_FB_H
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#if !CONFIG_IS_ENABLED(DM_VIDEO)
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#define HSVS_CONTROL BIT(25) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* opposite edges of pixel clock than
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* the lcd_pixel_o
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* 1 = lcd_lp and lcd_fp are driven
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* according to bit 24 Note that this
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* bit MUST be set to '0' for Passive
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* Matrix displays the edge timing is
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* fixed
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*/
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#define HSVS_RISEFALL BIT(24) /*
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* 0 = lcd_lp and lcd_fp are driven on
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* the rising edge of pixel clock (bit
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* 25 must be set to 1)
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* 1 = lcd_lp and lcd_fp are driven on
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* the falling edge of pixel clock (bit
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* 25 must be set to 1)
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*/
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#define DE_INVERT BIT(23) /*
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* 0 = DE is low-active
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* 1 = DE is high-active
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*/
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#define PXCLK_INVERT BIT(22) /*
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* 0 = pix-clk is high-active
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* 1 = pic-clk is low-active
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*/
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#define HSYNC_INVERT BIT(21) /*
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* 0 = HSYNC is active high
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* 1 = HSYNC is avtive low
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*/
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#define VSYNC_INVERT BIT(20) /*
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* 0 = VSYNC is active high
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* 1 = VSYNC is active low
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*/
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struct am335x_lcdpanel {
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unsigned int hactive; /* Horizontal active area */
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unsigned int vactive; /* Vertical active area */
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unsigned int bpp; /* bits per pixel */
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unsigned int hfp; /* Horizontal front porch */
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unsigned int hbp; /* Horizontal back porch */
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unsigned int hsw; /* Horizontal Sync Pulse Width */
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unsigned int vfp; /* Vertical front porch */
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unsigned int vbp; /* Vertical back porch */
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unsigned int vsw; /* Vertical Sync Pulse Width */
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unsigned int pxl_clk; /* Pixel clock */
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unsigned int pol; /* polarity of sync, clock signals */
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unsigned int pup_delay; /*
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* time in ms after power on to
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* initialization of lcd-controller
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* (VCC ramp up time)
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*/
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unsigned int pon_delay; /*
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* time in ms after initialization of
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* lcd-controller (pic stabilization)
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*/
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void (*panel_power_ctrl)(int); /* fp for power on/off display */
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};
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int am335xfb_init(struct am335x_lcdpanel *panel);
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#endif /* CONFIG_DM_VIDEO */
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#endif /* AM335X_FB_H */
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