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930c514d47
The size allocation for SPL is increased in all cases to match the
already-expanded value used on Tegra124. This is both for general
consistency, and because the seaboard build trips over the limit already
when using one of the ARM compilers packaged with 14.04. For the record,
when building Seaboard:
arm-linux-gnueabi- SPL is too big by 0x36 bytes
arm-linux-gnueabihf- SPL fits by 0x2a bytes
arm-none-eabi- SPL fits by 0xa bytes
(Those figures are from builds with the expanded SPL size allocation,
relative to the non-expanded SPL size limit; they're better by about
6 bytes in the more constrained build.)
Fixes: ba52199422 ("tegra124: Expand SPL space by 8KB")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
100 lines
3.1 KiB
C
100 lines
3.1 KiB
C
/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA20_COMMON_H_
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#define _TEGRA20_COMMON_H_
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#include "tegra-common.h"
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/* Cortex-A9 uses a cache line size of 32 bytes */
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/*
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* Errata configuration
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*/
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#define CONFIG_ARM_ERRATA_716044
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#define CONFIG_ARM_ERRATA_742230
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#define CONFIG_ARM_ERRATA_751472
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_STACKBASE 0x02800000 /* 40MB */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_SYS_TEXT_BASE 0x00110000
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/*
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* Memory layout for where various images get loaded by boot scripts:
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*
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* scriptaddr can be pretty much anywhere that doesn't conflict with something
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* else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
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* something else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* kernel_addr_r must be within the first 128M of RAM in order for the
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
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* should not overlap that area, or the kernel will have to copy itself
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* somewhere else before decompression. Similarly, the address of any other
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* data passed to the kernel shouldn't overlap the start of RAM. Pushing
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* this up to 16M allows for a sizable kernel to be decompressed below the
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* compressed load address.
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*
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* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
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* the compressed kernel to be up to 16M too.
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*
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* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
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* for the FDT/DTB to be up to 1M, which is hopefully plenty.
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*/
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#define CONFIG_LOADADDR 0x01000000
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=0x10000000\0" \
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"pxefile_addr_r=0x10100000\0" \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"fdt_addr_r=0x02000000\0" \
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"ramdisk_addr_r=0x02100000\0"
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x00108000
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#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
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#define CONFIG_SPL_STACK 0x000ffffc
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/* Align LCD to 1MB boundary */
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#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
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#ifdef CONFIG_TEGRA_LP0
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#define TEGRA_LP0_ADDR 0x1C406000
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#define TEGRA_LP0_SIZE 0x2000
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#define TEGRA_LP0_VEC \
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"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
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"@" __stringify(TEGRA_LP0_ADDR) " "
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#else
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#define TEGRA_LP0_VEC
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#endif
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/*
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* This parameter affects a TXFILLTUNING field that controls how much data is
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* sent to the latency fifo before it is sent to the wire. Without this
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* parameter, the default (2) causes occasional Data Buffer Errors in OUT
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* packets depending on the buffer address and size.
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*/
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#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
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#define CONFIG_SYS_NAND_SELF_INIT
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#endif /* _TEGRA20_COMMON_H_ */
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