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https://github.com/AsahiLinux/u-boot
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13194f3b5f
This adds driver layer for xHCI controller in Samsung's exynos5 soc. This interacts with xHCI host controller stack. Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/* Copyright (c) 2012 Samsung Electronics Co. Ltd
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*
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* Exynos Phy register definitions
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_XHCI_EXYNOS_H_
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#define _ASM_ARCH_XHCI_EXYNOS_H_
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/* Phy register MACRO definitions */
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#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
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#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
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#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
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#define PHYUTMI_OTGDISABLE (1 << 6)
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#define PHYUTMI_FORCESUSPEND (1 << 1)
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#define PHYUTMI_FORCESLEEP (1 << 0)
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#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
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#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
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#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
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#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
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#define PHYCLKRST_SSC_EN (0x1 << 20)
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#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
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#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
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#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
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#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
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#define PHYCLKRST_FSEL_MASK (0x3f << 5)
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#define PHYCLKRST_FSEL(_x) ((_x) << 5)
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#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
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#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
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#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
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#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
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#define PHYCLKRST_RETENABLEN (0x1 << 4)
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#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
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#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
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#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
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#define PHYCLKRST_PORTRESET (0x1 << 1)
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#define PHYCLKRST_COMMONONN (0x1 << 0)
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#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
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#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
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#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
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#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
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#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
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#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
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#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
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#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
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#define FSEL_CLKSEL_24M (0x5)
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/* XHCI PHY register structure */
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struct exynos_usb3_phy {
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unsigned int reserve1;
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unsigned int link_system;
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unsigned int phy_utmi;
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unsigned int phy_pipe;
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unsigned int phy_clk_rst;
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unsigned int phy_reg0;
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unsigned int phy_reg1;
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unsigned int phy_param0;
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unsigned int phy_param1;
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unsigned int phy_term;
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unsigned int phy_test;
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unsigned int phy_adp;
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unsigned int phy_batchg;
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unsigned int phy_resume;
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unsigned int reserve2[3];
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unsigned int link_port;
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};
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#endif /* _ASM_ARCH_XHCI_EXYNOS_H_ */
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