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0f62bf633f
In common usecases flush_cache() assumes both cache invalidation and write-back to memory, instead of doing cache invalidation only with the wrapped 'ocbi' instruction pin flush_cache() to cache invalidation with memory write-back done by 'ocbp'. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
83 lines
1.1 KiB
C
83 lines
1.1 KiB
C
/*
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* (C) Copyright 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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int checkcpu(void)
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{
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puts("CPU: SH4\n");
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return 0;
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}
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int cpu_init (void)
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{
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return 0;
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}
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int cleanup_before_linux (void)
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{
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disable_interrupts();
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return 0;
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}
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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reset_cpu (0);
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return 0;
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}
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void flush_cache (unsigned long addr, unsigned long size)
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{
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flush_dcache_range(addr , addr + size);
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}
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void icache_enable (void)
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{
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cache_control(0);
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}
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void icache_disable (void)
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{
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cache_control(1);
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}
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int icache_status (void)
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{
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return 0;
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}
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void dcache_enable (void)
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{
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}
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void dcache_disable (void)
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{
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}
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int dcache_status (void)
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{
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return 0;
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}
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int cpu_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SH_ETHER
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sh_eth_initialize(bis);
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#endif
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return 0;
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}
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void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
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{
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/* TODO(sh maintainer): Implement this */
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while (1);
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}
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