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https://github.com/AsahiLinux/u-boot
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c21f58548c
For LD11 and LD20 SoCs, the RST_n pin is asserted by default. If the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device would stay in the reset state until its RST_n pin is deasserted by software. Currently, this is cared by an ad-hoc way because the eMMC hardware reset provider is not supported in U-Boot for now. This code should be re-written once the "mmc-pwrseq-emmc" binding is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
45 lines
960 B
C
45 lines
960 B
C
/*
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* Copyright (C) 2016 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc64-regs.h"
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#include "../sg-regs.h"
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#define SDCTRL_EMMC_HW_RESET 0x59810280
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void uniphier_ld11_clk_init(void)
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{
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/* if booted from a device other than USB, without stand-by MPU */
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if ((readl(SG_PINMON0) & BIT(27)) &&
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uniphier_boot_device_raw() != BOOT_DEVICE_USB) {
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writel(1, SG_ETPHYPSHUT);
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writel(1, SG_ETPHYCNT);
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udelay(1); /* wait for regulator level 1.1V -> 2.5V */
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writel(3, SG_ETPHYCNT);
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writel(3, SG_ETPHYPSHUT);
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writel(7, SG_ETPHYCNT);
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}
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/* TODO: use "mmc-pwrseq-emmc" */
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writel(1, SDCTRL_EMMC_HW_RESET);
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#ifdef CONFIG_USB_EHCI
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{
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/* FIXME: the current clk driver can not handle parents */
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u32 tmp;
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tmp = readl(SC_CLKCTRL4);
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tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
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writel(tmp, SC_CLKCTRL4);
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}
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#endif
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}
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