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0f3d6b06ea
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> |
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common | ||
da8xxevm | ||
dm355evm | ||
dm355leopard | ||
dm365evm | ||
dm6467evm | ||
dvevm | ||
ea20 | ||
schmoogie | ||
sffsdr | ||
sonata |