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https://github.com/AsahiLinux/u-boot
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7870a05581
Add pcie driver for StarFive JH7110, Also add PLDA PCIe controller common driver functions. Several devices are tested: a) M.2 NVMe SSD b) Realtek 8169 Ethernet adapter. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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* Author: Minda Chen <minda.chen@starfivetech.com>
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*
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*/
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#ifndef PCIE_PLDA_COMMON_H
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#define PCIE_PLDA_COMMON_H
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#define GEN_SETTINGS 0x80
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#define PCIE_PCI_IDS 0x9C
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#define PCIE_WINROM 0xFC
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#define PMSG_SUPPORT_RX 0x3F0
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#define PCI_MISC 0xB4
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#define PLDA_EP_ENABLE 0
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#define PLDA_RP_ENABLE 1
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#define IDS_CLASS_CODE_SHIFT 8
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#define PREF_MEM_WIN_64_SUPPORT BIT(3)
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#define PMSG_LTR_SUPPORT BIT(2)
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#define PLDA_FUNCTION_DIS BIT(15)
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#define PLDA_FUNC_NUM 4
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#define PLDA_PHY_FUNC_SHIFT 9
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#define XR3PCI_ATR_AXI4_SLV0 0x800
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#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
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#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
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#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
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#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
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#define XR3PCI_ATR_TRSL_PARAM 0x10
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#define XR3PCI_ATR_TABLE_OFFSET 0x20
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#define XR3PCI_ATR_MAX_TABLE_NUM 8
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#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
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#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
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#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
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#define XR3PCI_ATR_TRSL_DIR BIT(22)
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/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
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#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
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#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
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/**
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* struct pcie_plda - PLDA PCIe controller state
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*
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* @reg_base: The base address of controller register space
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* @cfg_base: The base address of configuration space
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* @cfg_size: The size of configuration space
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* @sec_busno: Secondary bus number.
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* @atr_table_num: Total ATR table numbers.
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*/
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struct pcie_plda {
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struct udevice *dev;
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void __iomem *reg_base;
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void __iomem *cfg_base;
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phys_size_t cfg_size;
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int sec_busno;
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int atr_table_num;
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};
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int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size);
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int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size);
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int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
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phys_addr_t trsl_addr, phys_size_t window_size,
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int trsl_param);
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static inline void plda_pcie_enable_root_port(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + GEN_SETTINGS);
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value |= PLDA_RP_ENABLE;
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writel(value, plda->reg_base + GEN_SETTINGS);
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}
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static inline void plda_pcie_set_standard_class(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + PCIE_PCI_IDS);
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value &= 0xff;
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value |= (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT);
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writel(value, plda->reg_base + PCIE_PCI_IDS);
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}
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static inline void plda_pcie_set_pref_win_64bit(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + PCIE_WINROM);
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value |= PREF_MEM_WIN_64_SUPPORT;
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writel(value, plda->reg_base + PCIE_WINROM);
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}
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static inline void plda_pcie_disable_ltr(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + PMSG_SUPPORT_RX);
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value &= ~PMSG_LTR_SUPPORT;
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writel(value, plda->reg_base + PMSG_SUPPORT_RX);
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}
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static inline void plda_pcie_disable_func(struct pcie_plda *plda)
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{
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u32 value;
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value = readl(plda->reg_base + PCI_MISC);
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value |= PLDA_FUNCTION_DIS;
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writel(value, plda->reg_base + PCI_MISC);
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}
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#endif
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