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c13fe7c034
Add a DM clock driver for StarFive JH7110 SoC. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
57 lines
1.1 KiB
C
57 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022 Starfive, Inc.
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* Author: Yanhong Wang <yanhong.wang@starfivetech.com>
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*
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*/
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#ifndef __CLK_STARFIVE_H
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#define __CLK_STARFIVE_H
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enum starfive_pll_type {
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PLL0 = 0,
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PLL1,
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PLL2,
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PLL_MAX = PLL2
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};
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struct starfive_pllx_rate {
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u64 rate;
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u32 prediv;
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u32 fbdiv;
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u32 frac;
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};
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struct starfive_pllx_offset {
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u32 pd;
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u32 prediv;
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u32 fbdiv;
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u32 frac;
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u32 postdiv1;
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u32 dacpd;
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u32 dsmpd;
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u32 pd_mask;
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u32 prediv_mask;
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u32 fbdiv_mask;
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u32 frac_mask;
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u32 postdiv1_mask;
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u32 dacpd_mask;
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u32 dsmpd_mask;
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};
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struct starfive_pllx_clk {
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enum starfive_pll_type type;
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const struct starfive_pllx_offset *offset;
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const struct starfive_pllx_rate *rate_table;
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int rate_count;
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int flags;
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};
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extern struct starfive_pllx_clk starfive_jh7110_pll0;
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extern struct starfive_pllx_clk starfive_jh7110_pll1;
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extern struct starfive_pllx_clk starfive_jh7110_pll2;
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struct clk *starfive_jh7110_pll(const char *name, const char *parent_name,
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void __iomem *base, void __iomem *sysreg,
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const struct starfive_pllx_clk *pll_clk);
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#endif
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