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https://github.com/AsahiLinux/u-boot
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917cfc70c1
http://www.denx.de/wiki/DULG/UBootCmdGroupFlash#UBootCmdFlMtdparts provides a flexible way to create and maintain u-boot mtd partitions. This allows commands such as "nand erase fs" to work and the user no longer needs to decode the absolute nand offsets. This patch enables this function for beagleboard Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
330 lines
10 KiB
C
330 lines
10 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments.
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <x0khasim@ti.com>
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*
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* Configuration settings for the TI OMAP3530 Beagle board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/sizes.h>
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
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#define CONFIG_OMAP 1 /* in a TI OMAP core */
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#define CONFIG_OMAP34XX 1 /* which is a 34XX */
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#define CONFIG_OMAP3430 1 /* which is in a 3430 */
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#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap3.h>
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#undef CONFIG_USE_IRQ /* no support for IRQs */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */
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/* Sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
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/* initial data */
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 3
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_MMC 1
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#define CONFIG_OMAP3_MMC 1
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#define CONFIG_DOS_PARTITION 1
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/* commands to include */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
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#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
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#define MTDIDS_DEFAULT "nand0=nand"
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#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
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"1920k(u-boot),128k(u-boot-env),"\
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"4m(kernel),-(fs)"
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_NAND /* NAND support */
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#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
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#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
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#undef CONFIG_CMD_IMI /* iminfo */
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#undef CONFIG_CMD_IMLS /* List all found images */
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#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#undef CONFIG_CMD_NFS /* NFS support */
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 1
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#define CONFIG_SYS_I2C_BUS 0
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#define CONFIG_SYS_I2C_BUS_SELECT 1
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#define CONFIG_DRIVER_OMAP34XX_I2C 1
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/*
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* Board NAND Info.
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*/
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access nand at */
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/* CS0 */
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#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
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/* devices */
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#define SECTORSIZE 512
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#define NAND_ALLOW_ERASE_ALL
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define NAND_NO_RB 1
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#define CONFIG_SYS_NAND_WP
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
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/* partition */
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/* Environment information */
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#define CONFIG_BOOTDELAY 10
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyS2,115200n8\0" \
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"videomode=1024x768@60,vxres=1024,vyres=768\0" \
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"videospec=omapfb:vram:2M,vram:4M\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"video=${videospec},mode:${videomode} " \
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"root=/dev/mmcblk0p2 rw " \
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"rootfstype=ext3 rootwait\0" \
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"nandargs=setenv bootargs console=${console} " \
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"video=${videospec},mode:${videomode} " \
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"root=/dev/mtdblock4 rw " \
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"rootfstype=jffs2\0" \
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"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"autoscr ${loadaddr}\0" \
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"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} 280000 400000; " \
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"bootm ${loadaddr}\0" \
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#define CONFIG_BOOTCOMMAND \
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"if mmcinit; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run nandboot; " \
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"fi; " \
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"fi; " \
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"else run nandboot; fi"
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#define CONFIG_AUTO_COMPLETE 1
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/*
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* Miscellaneous configurable options
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*/
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#define V_PROMPT "OMAP3 beagleboard.org # "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT V_PROMPT
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
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/* works on */
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
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/* load address */
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/*
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* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
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* 32KHz clk, or from external sig. This rate is divided by a local divisor.
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*/
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#define V_PVT 7
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
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#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE SZ_128K /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/* SDRAM Bank Allocation method */
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#define SDRC_R_B_C 1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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/* Configure the PISMO */
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#define PISMO1_NAND_SIZE GPMC_SIZE_128M
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#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
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#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
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/* one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
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#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */
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#define CONFIG_SYS_FLASH_BASE boot_flash_base
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
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#define CONFIG_ENV_IS_IN_NAND 1
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#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
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#define CONFIG_ENV_OFFSET boot_flash_off
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#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
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/* Flash banks JFFS2 should use */
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#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
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CONFIG_SYS_MAX_NAND_DEVICE)
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#define CONFIG_SYS_JFFS2_MEM_NAND
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/* use flash_info[2] */
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#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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#ifndef __ASSEMBLY__
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extern gpmc_csx_t *nand_cs_base;
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extern gpmc_t *gpmc_cfg_base;
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extern unsigned int boot_flash_base;
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extern volatile unsigned int boot_flash_env_addr;
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extern unsigned int boot_flash_off;
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extern unsigned int boot_flash_sec;
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extern unsigned int boot_flash_type;
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#endif
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#define WRITE_NAND_COMMAND(d, adr)\
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writel(d, &nand_cs_base->nand_cmd)
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#define WRITE_NAND_ADDRESS(d, adr)\
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writel(d, &nand_cs_base->nand_adr)
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#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
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#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
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/* Other NAND Access APIs */
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#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
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while (0)
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#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
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while (0)
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#define NAND_DISABLE_CE(nand)
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#define NAND_ENABLE_CE(nand)
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#define NAND_WAIT_READY(nand) udelay(10)
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#endif /* __CONFIG_H */
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