York Sun c107c0c05c armv8: fsl-layerscape: Make DDR non secure in MMU tables ... DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>		2015-12-15 08:57:33 +08:00
..
clock.h
config.h	armv8: fsl-layerscape: Make DDR non secure in MMU tables	2015-12-15 08:57:33 +08:00
cpu.h	armv8: fsl-layerscape: Make DDR non secure in MMU tables	2015-12-15 08:57:33 +08:00
fdt.h	armv8/ls1043aqds: add LS1043AQDS board support	2015-11-30 09:11:10 -08:00
fsl_serdes.h	armv8: ls2085a: Add support of LS2085A SoC	2015-11-30 09:10:47 -08:00
immap_lsch2.h	armv8/ls1043ardb: add USB support	2015-11-30 09:11:11 -08:00
immap_lsch3.h	pci/layerscape: add support for LS1043A PCIe LUT register access	2015-11-30 09:11:10 -08:00
imx-regs.h
ls2080a_stream_id.h	armv8: LS2080A: Rename LS2085A to reflect LS2080A	2015-11-30 08:53:04 -08:00
mmu.h
mp.h
ns_access.h	armv8/fsl_lsch2: Add fsl_lsch2 SoC	2015-10-29 10:34:00 -07:00
soc.h	armv8: ls2085a: Add workaround of errata A009635	2015-11-30 09:11:12 -08:00
speed.h