u-boot/configs/T2080QDS_SPIFLASH_defconfig
Pali Rohár c0f4756216 powerpc: mpc85xx: Set TEXT_BASE addresses to real base values
Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are
manually increased by 0x1000 due to .bootpg section. This section has size
of 0x1000 bytes and is manually put by linker script before .text section
(and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is
set. Due to this fact lot of other config options are manually increased by
0x1000 value to make correct layout. Note that entry point is not on
CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address
CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image).

Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is
set. Put .bootpg code directly into .text section and move text base
address to the start of .bootpg code. And finally remove +0x1000 value from
lot of config options. With this removal custom PHDRS is not used anymore,
so remove it too.

After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at
address -0x1000 anymore.

Tested on P2020 board with SPL and proper U-Boot.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-06-28 09:40:02 -04:00

128 lines
3.6 KiB
Text

CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_SPL_TEXT_BASE=0xFFFD8000
CONFIG_FSL_USE_PCA9547_MUX=y
CONFIG_VID=y
CONFIG_VID_FLS_ENV="t208xqds_vdd_mv"
CONFIG_VOL_MONITOR_IR36021_READ=y
CONFIG_VOL_MONITOR_IR36021_SET=y
CONFIG_FSL_QIXIS=y
# CONFIG_QIXIS_I2C_ACCESS is not set
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_DYNAMIC_SYS_CLK_FREQ=y
CONFIG_RAMBOOT_PBL=y
CONFIG_SPIFLASH=y
CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xqds/t208x_pbi.cfg"
CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xqds/t2080_spi_rcw.cfg"
CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MAX_SIZE=0x28000
CONFIG_SPL_PAD_TO=0x40000
CONFIG_SPL_SPI_BOOT=y
CONFIG_SPL_FSL_PBL=y
CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
CONFIG_SPL_FLUSH_IMAGE=y
CONFIG_SPL_SKIP_RELOCATE=y
CONFIG_SPL_GD_ADDR=0xfffc8000
CONFIG_SPL_RELOC_STACK=0xfffd8000
CONFIG_SPL_RELOC_MALLOC=y
CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000
CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C=y
CONFIG_SPL_MPC8XXX_INIT_DDR=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_BOOTFILE=y
CONFIG_BOOTFILE="uImage"
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x118000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SYS_MAX_FLASH_BANKS=2
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_SYS_FMAN_FW_ADDR=0x110000
CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64