mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
c0f4756216
Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are manually increased by 0x1000 due to .bootpg section. This section has size of 0x1000 bytes and is manually put by linker script before .text section (and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Due to this fact lot of other config options are manually increased by 0x1000 value to make correct layout. Note that entry point is not on CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image). Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Put .bootpg code directly into .text section and move text base address to the start of .bootpg code. And finally remove +0x1000 value from lot of config options. With this removal custom PHDRS is not used anymore, so remove it too. After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at address -0x1000 anymore. Tested on P2020 board with SPL and proper U-Boot. Signed-off-by: Pali Rohár <pali@kernel.org>
113 lines
2.2 KiB
Text
113 lines
2.2 KiB
Text
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2007-2009, 2011 Freescale Semiconductor, Inc.
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*/
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#include "config.h"
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#ifdef CONFIG_RESET_VECTOR_ADDRESS
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#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
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#else
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#define RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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OUTPUT_ARCH(powerpc)
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ENTRY(_start)
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SECTIONS
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{
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/* Read-only sections, merged into text segment: */
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.text :
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{
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#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
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KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
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#endif
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*(.text*)
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}
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_etext = .;
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PROVIDE (etext = .);
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.rodata :
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{
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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}
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/* Read-write section, merged into data segment: */
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. = (. + 0x00FF) & 0xFFFFFF00;
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_erotext = .;
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PROVIDE (erotext = .);
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.reloc :
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{
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_GOT2_TABLE_ = .;
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KEEP(*(.got2))
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KEEP(*(.got))
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_FIXUP_TABLE_ = .;
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KEEP(*(.fixup))
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}
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__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
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.data :
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{
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*(.data*)
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*(.sdata*)
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}
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_edata = .;
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PROVIDE (edata = .);
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. = .;
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. = ALIGN(4);
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__u_boot_list : {
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KEEP(*(SORT(__u_boot_list*)));
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}
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. = .;
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__start___ex_table = .;
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__ex_table : { *(__ex_table) }
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__stop___ex_table = .;
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. = ALIGN(4);
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__init_begin = .;
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.text.init : { *(.text.init) }
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.data.init : { *(.data.init) }
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. = ALIGN(4);
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__init_end = .;
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_end = .;
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#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC
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.bootpg RESET_VECTOR_ADDRESS - 0xffc :
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{
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arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
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} = 0xffff
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.resetvec RESET_VECTOR_ADDRESS :
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{
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KEEP(*(.resetvec))
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} = 0xffff
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. = RESET_VECTOR_ADDRESS + 0x4;
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/*
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* Make sure that the bss segment isn't linked at 0x0, otherwise its
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* address won't be updated during relocation fixups. Note that
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* this is a temporary fix. Code to dynamically the fixup the bss
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* location will be added in the future. When the bss relocation
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* fixup code is present this workaround should be removed.
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*/
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#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
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. |= 0x10;
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#endif
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#endif
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__bss_start = .;
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.bss (NOLOAD) :
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{
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*(.sbss*)
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*(.bss*)
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*(COMMON)
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}
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. = ALIGN(4);
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__bss_end = . ;
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PROVIDE (end = .);
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}
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