mirror of
https://github.com/AsahiLinux/u-boot
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ab5814f992
CONFIG_SYS_NAND_ADDR is defined and never referenced. This patch removes the dead code. Signed-off-by: Adam Ford <aford173@gmail.com>
263 lines
7.4 KiB
C
263 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* am3517_crane.h - Default configuration for AM3517 CraneBoard.
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*
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* Author: Srinath.R <srinath@mistralsolutions.com>
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*
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* Based on include/configs/am3517evm.h
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*
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* Copyright (C) 2011 Mistral Solutions pvt Ltd
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#include <asm/arch/omap.h>
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_REVISION_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
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/* initial data */
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/*
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* DDR related
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*/
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#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
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/*
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* Hardware drivers
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*/
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/*
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* NS16550 Configuration
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*/
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#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* select serial console configuration
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*/
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#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
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#define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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/*
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* USB configuration
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* Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
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* Enable CONFIG_USB_MUSB_UDC for Device functionalities.
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*/
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#ifdef CONFIG_USB_AM35X
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#ifdef CONFIG_USB_MUSB_HCD
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#ifdef CONFIG_USB_KEYBOARD
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#define CONFIG_PREBOOT "usb start"
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#endif /* CONFIG_USB_KEYBOARD */
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#endif /* CONFIG_USB_MUSB_HCD */
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#ifdef CONFIG_USB_MUSB_UDC
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/* USB device configuration */
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#define CONFIG_USB_DEVICE 1
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#define CONFIG_USB_TTY 1
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/* Change these to suit your needs */
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#define CONFIG_USBD_VENDORID 0x0451
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#define CONFIG_USBD_PRODUCTID 0x5678
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#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
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#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
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#endif /* CONFIG_USB_MUSB_UDC */
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#endif /* CONFIG_USB_AM35X */
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#define CONFIG_SYS_I2C
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
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/* to access */
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/* nand at CS0 */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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/* NAND devices */
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#define CONFIG_JFFS2_NAND
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/* nand device jffs2 lives on */
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#define CONFIG_JFFS2_DEV "nand0"
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/* start of jffs2 partition */
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#define CONFIG_JFFS2_PART_OFFSET 0x680000
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#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
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/* Environment information */
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x82000000\0" \
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"console=ttyS2,115200n8\0" \
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"mmcdev=0\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"root=/dev/mmcblk0p2 rw " \
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"rootfstype=ext3 rootwait\0" \
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"nandargs=setenv bootargs console=${console} " \
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"root=/dev/mtdblock4 rw " \
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"rootfstype=jffs2\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source ${loadaddr}\0" \
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"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm ${loadaddr}\0" \
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"nandboot=echo Booting from nand ...; " \
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"run nandargs; " \
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"nand read ${loadaddr} 280000 400000; " \
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"bootm ${loadaddr}\0" \
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run nandboot; " \
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"fi; " \
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"fi; " \
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"else run nandboot; fi"
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 32 /* max number of command */
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/* args */
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
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/* address */
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/*
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* AM3517 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/* **** PISMO SUPPORT *** */
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#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
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/* on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#define CONFIG_SYS_FLASH_BASE NAND_BASE
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
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#define CONFIG_ENV_OFFSET 0x260000
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#define CONFIG_ENV_ADDR 0x260000
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
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/* Flash banks JFFS2 should use */
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#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
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CONFIG_SYS_MAX_NAND_DEVICE)
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#define CONFIG_SYS_JFFS2_MEM_NAND
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/* use flash_info[2] */
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#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
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#define CONFIG_SYS_JFFS2_NUM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
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#define CONFIG_SYS_INIT_RAM_SIZE 0x800
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/* Defines for SPL */
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#define CONFIG_SPL_TEXT_BASE 0x40200800
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#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
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CONFIG_SPL_TEXT_BASE)
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_ECC
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/* NAND boot config */
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
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10, 11, 12, 13}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 3
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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* 64 bytes before this address should be set aside for u-boot.img's
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* header. That is 0x800FFFC0--0x80100000 should not be used for any
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* other needs.
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*/
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#endif /* __CONFIG_H */
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