mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 23:02:59 +00:00
f7ae49fc4f
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
313 lines
7.6 KiB
C
313 lines
7.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Samsung Electronics
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*/
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#include <common.h>
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#include <config.h>
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#include <init.h>
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#include <log.h>
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#include <asm/cache.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/dmc.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/spi.h>
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#include "common_setup.h"
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#include "clock_init.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* Index into irom ptr table */
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enum index {
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MMC_INDEX,
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EMMC44_INDEX,
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EMMC44_END_INDEX,
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SPI_INDEX,
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USB_INDEX,
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};
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/* IROM Function Pointers Table */
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u32 irom_ptr_table[] = {
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[MMC_INDEX] = 0x02020030, /* iROM Function Pointer-SDMMC boot */
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[EMMC44_INDEX] = 0x02020044, /* iROM Function Pointer-EMMC4.4 boot*/
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[EMMC44_END_INDEX] = 0x02020048,/* iROM Function Pointer
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-EMMC4.4 end boot operation */
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[SPI_INDEX] = 0x02020058, /* iROM Function Pointer-SPI boot */
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[USB_INDEX] = 0x02020070, /* iROM Function Pointer-USB boot*/
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};
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void *get_irom_func(int index)
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{
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return (void *)*(u32 *)irom_ptr_table[index];
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}
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#ifdef CONFIG_USB_BOOTING
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/*
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* Set/clear program flow prediction and return the previous state.
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*/
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static int config_branch_prediction(int set_cr_z)
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{
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unsigned int cr;
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/* System Control Register: 11th bit Z Branch prediction enable */
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cr = get_cr();
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set_cr(set_cr_z ? cr | CR_Z : cr & ~CR_Z);
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return cr & CR_Z;
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}
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#endif
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#ifdef CONFIG_SPI_BOOTING
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static void spi_rx_tx(struct exynos_spi *regs, int todo,
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void *dinp, void const *doutp, int i)
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{
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uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
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int rx_lvl, tx_lvl;
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uint out_bytes, in_bytes;
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out_bytes = todo;
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in_bytes = todo;
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setbits_le32(®s->ch_cfg, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
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while (in_bytes) {
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uint32_t spi_sts;
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int temp;
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spi_sts = readl(®s->spi_sts);
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rx_lvl = ((spi_sts >> 15) & 0x7f);
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tx_lvl = ((spi_sts >> 6) & 0x7f);
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while (tx_lvl < 32 && out_bytes) {
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temp = 0xffffffff;
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writel(temp, ®s->tx_data);
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out_bytes -= 4;
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tx_lvl += 4;
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}
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while (rx_lvl >= 4 && in_bytes) {
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temp = readl(®s->rx_data);
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if (rxp)
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*rxp++ = temp;
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in_bytes -= 4;
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rx_lvl -= 4;
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}
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}
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}
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/*
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* Copy uboot from spi flash to RAM
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*
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* @parma uboot_size size of u-boot to copy
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* @param uboot_addr address in u-boot to copy
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*/
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static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
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{
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int upto, todo;
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int i, timeout = 100;
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struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE;
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set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
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/* set the spi1 GPIO */
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exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
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/* set pktcnt and enable it */
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writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
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/* set FB_CLK_SEL */
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writel(SPI_FB_DELAY_180, ®s->fb_clk);
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/* set CH_WIDTH and BUS_WIDTH as word */
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setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
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SPI_MODE_BUS_WIDTH_WORD);
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clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
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/* clear rx and tx channel if set priveously */
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clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
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setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN |
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SPI_RX_BYTE_SWAP |
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SPI_RX_HWORD_SWAP);
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/* do a soft reset */
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setbits_le32(®s->ch_cfg, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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/* now set rx and tx channel ON */
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setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
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clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
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/* Send read instruction (0x3h) followed by a 24 bit addr */
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writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data);
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/* waiting for TX done */
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while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) {
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if (!timeout) {
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debug("SPI TIMEOUT\n");
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break;
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}
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timeout--;
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}
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for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
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todo = min(uboot_size - upto, (unsigned int)(1 << 15));
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spi_rx_tx(regs, todo, (void *)(uboot_addr),
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(void *)(SPI_FLASH_UBOOT_POS), i);
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}
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setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
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/*
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* Let put controller mode to BYTE as
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* SPI driver does not support WORD mode yet
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*/
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clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
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SPI_MODE_BUS_WIDTH_WORD);
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writel(0, ®s->swap_cfg);
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/*
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* Flush spi tx, rx fifos and reset the SPI controller
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* and clear rx/tx channel
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*/
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clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_CH_RST);
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clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
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}
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#endif
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/*
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* Copy U-Boot from mmc to RAM:
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* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
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* Pointer to API (Data transfer from mmc to ram)
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*/
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void copy_uboot_to_ram(void)
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{
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unsigned int bootmode = BOOT_MODE_OM;
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u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
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u32 offset = 0, size = 0;
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#ifdef CONFIG_SPI_BOOTING
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struct spl_machine_param *param = spl_get_machine_params();
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#endif
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#ifdef CONFIG_SUPPORT_EMMC_BOOT
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u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
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void (*end_bootop_from_emmc)(void);
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#endif
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#ifdef CONFIG_USB_BOOTING
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int is_cr_z_set;
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unsigned int sec_boot_check;
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/*
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* Note that older hardware (before Exynos5800) does not expect any
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* arguments, but it does not hurt to pass them, so a common function
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* prototype is used.
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*/
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u32 (*usb_copy)(u32 num_of_block, u32 *dst);
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/* Read iRAM location to check for secondary USB boot mode */
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sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
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if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
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bootmode = BOOT_MODE_USB;
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#endif
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if (bootmode == BOOT_MODE_OM)
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bootmode = get_boot_mode();
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switch (bootmode) {
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#ifdef CONFIG_SPI_BOOTING
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case BOOT_MODE_SERIAL:
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/* Customised function to copy u-boot from SF */
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exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
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break;
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#endif
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case BOOT_MODE_SD:
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offset = BL2_START_OFFSET;
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size = BL2_SIZE_BLOC_COUNT;
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copy_bl2 = get_irom_func(MMC_INDEX);
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break;
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#ifdef CONFIG_SUPPORT_EMMC_BOOT
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case BOOT_MODE_EMMC:
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/* Set the FSYS1 clock divisor value for EMMC boot */
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emmc_boot_clk_div_set();
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copy_bl2_from_emmc = get_irom_func(EMMC44_INDEX);
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end_bootop_from_emmc = get_irom_func(EMMC44_END_INDEX);
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copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
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end_bootop_from_emmc();
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break;
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#endif
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#ifdef CONFIG_USB_BOOTING
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case BOOT_MODE_USB:
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/*
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* iROM needs program flow prediction to be disabled
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* before copy from USB device to RAM
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*/
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is_cr_z_set = config_branch_prediction(0);
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usb_copy = get_irom_func(USB_INDEX);
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usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE);
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config_branch_prediction(is_cr_z_set);
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break;
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#endif
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default:
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break;
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}
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if (copy_bl2)
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copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
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}
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void memzero(void *s, size_t n)
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{
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char *ptr = s;
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size_t i;
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for (i = 0; i < n; i++)
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*ptr++ = '\0';
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}
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/**
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* Set up the U-Boot global_data pointer
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*
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* This sets the address of the global data, and sets up basic values.
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*
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* @param gdp Value to give to gd
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*/
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static void setup_global_data(gd_t *gdp)
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{
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gd = gdp;
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memzero((void *)gd, sizeof(gd_t));
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gd->flags |= GD_FLG_RELOC;
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gd->baudrate = CONFIG_BAUDRATE;
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gd->have_console = 1;
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}
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void board_init_f(unsigned long bootflag)
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{
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__aligned(8) gd_t local_gd;
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__attribute__((noreturn)) void (*uboot)(void);
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setup_global_data(&local_gd);
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if (do_lowlevel_init())
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power_exit_wakeup();
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copy_uboot_to_ram();
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/* Jump to U-Boot image */
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uboot = (void *)CONFIG_SYS_TEXT_BASE;
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(*uboot)();
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/* Never returns Here */
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}
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/* Place Holders */
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void board_init_r(gd_t *id, ulong dest_addr)
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{
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/* Function attribute is no-return */
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/* This Function never executes */
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while (1)
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;
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}
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