mirror of
https://github.com/AsahiLinux/u-boot
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7a577fda22
Rather than defining it config.mk we can set it in config.h and remove config.mk from several boards that don't need it. We mimic what 4xx does and introduce CONFIG_RESET_VECTOR_ADDRESS for config.h to set. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
726 lines
23 KiB
C
726 lines
23 KiB
C
/*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* p2020ds board configuration file
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "../board/freescale/common/ics307_clk.h"
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#ifdef CONFIG_36BIT
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#define CONFIG_PHYS_64BIT
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
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#define CONFIG_P2020 1
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#define CONFIG_P2020DS 1
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#define CONFIG_MP 1 /* support multiple processors */
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff80000
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#endif
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_SRIO2 /* SRIO port 2 */
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#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
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#define CONFIG_PCI 1 /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
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#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
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#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP 1
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
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#else
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
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#endif
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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/* DDR Setup */
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#define CONFIG_VERY_BIG_RAM
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#ifdef CONFIG_DDR2
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#define CONFIG_FSL_DDR2
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#else
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#define CONFIG_FSL_DDR3 1
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#endif
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#undef CONFIG_FSL_DDR_INTERACTIVE
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/* ECC will be enabled based on perf_mode environment variable */
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/* #define CONFIG_DDR_ECC */
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 2
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/* I2C addresses of SPD EEPROMs */
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#define CONFIG_DDR_SPD
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#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */
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#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
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/* These are used when DDR doesn't use SPD. */
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#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */
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/* Default settings for "stable" mode */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
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#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
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#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
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#define CONFIG_SYS_DDR_TIMING_3 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0 0x00330804
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#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846
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#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4
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#define CONFIG_SYS_DDR_MODE_1 0x00421422
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#define CONFIG_SYS_DDR_MODE_2 0x00000000
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#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL 0x61800100
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
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#define CONFIG_SYS_DDR_TIMING_4 0x00220001
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#define CONFIG_SYS_DDR_TIMING_5 0x03402400
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#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
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#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608
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#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
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#define CONFIG_SYS_DDR_CONTROL2 0x24400011
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#define CONFIG_SYS_DDR_CDR1 0x00040000
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#define CONFIG_SYS_DDR_CDR2 0x00000000
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#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
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#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
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#define CONFIG_SYS_DDR_SBE 0x00010000
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/* Settings that differ for "performance" mode */
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#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */
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#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */
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#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202
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#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543
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#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce
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#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
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/*
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* The following set of values were tested for DDR2
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* with a DDR3 to DDR2 interposer
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*
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
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#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
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#define CONFIG_SYS_DDR_MODE_1 0x00480432
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#define CONFIG_SYS_DDR_MODE_2 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL 0x06180100
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#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
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#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
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#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
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#define CONFIG_SYS_DDR_CONTROL 0xC3008000
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#define CONFIG_SYS_DDR_CONTROL2 0x04400010
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*
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*/
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
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* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
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* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
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* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
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*
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* Localbus cacheable (TBD)
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* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
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*
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* Localbus non-cacheable
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* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
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* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
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* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
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* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
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* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
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*/
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/*
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* Local Bus Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
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#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
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#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
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#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
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#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
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#define CONFIG_HWCONFIG /* enable hwconfig */
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#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
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#ifdef CONFIG_FSL_NGPIXIS
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#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
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#ifdef CONFIG_PHYS_64BIT
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#define PIXIS_BASE_PHYS 0xfffdf0000ull
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#else
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#define PIXIS_BASE_PHYS PIXIS_BASE
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#endif
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#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
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#define PIXIS_LBMAP_SWITCH 7
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#define PIXIS_LBMAP_MASK 0xf0
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#define PIXIS_LBMAP_SHIFT 4
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#define PIXIS_LBMAP_ALTBANK 0x20
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#endif
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
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#endif
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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#define CONFIG_SYS_NAND_BASE 0xffa00000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
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#else
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#endif
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
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CONFIG_SYS_NAND_BASE + 0x40000, \
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CONFIG_SYS_NAND_BASE + 0x80000,\
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CONFIG_SYS_NAND_BASE + 0xC0000}
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#define CONFIG_SYS_MAX_NAND_DEVICE 4
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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/* NAND flash config */
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#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
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| OR_FCM_PGS /* Large Page*/ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
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#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
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#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
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#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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/*
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* Pass open firmware flat tree
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*/
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/* I2C */
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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/*
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* I2C2 EEPROM
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*/
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#define CONFIG_ID_EEPROM
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#ifdef CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#endif
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 3, Slot 1, tgtid 3, Base address b000 */
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#define CONFIG_SYS_PCIE3_NAME "Slot 1"
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
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#else
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
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#endif
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, direct to uli, tgtid 2, Base address 9000 */
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#define CONFIG_SYS_PCIE2_NAME "ULI"
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
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#else
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
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#endif
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 1, Slot 2, tgtid 1, Base address a000 */
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#define CONFIG_SYS_PCIE1_NAME "Slot 2"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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#if defined(CONFIG_PCI)
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/*PCIE video card used*/
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#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
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/* video */
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#define CONFIG_VIDEO
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#if defined(CONFIG_VIDEO)
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#define CONFIG_BIOSEMU
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_ATI_RADEON_FB
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#define CONFIG_VIDEO_LOGO
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/*#define CONFIG_CONSOLE_CURSOR*/
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
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#endif
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/* SRIO1 uses the same window as PCIE2 mem window */
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
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/* SRIO2 uses the same window as PCIE1 mem window */
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#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
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#else
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#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
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#endif
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#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#define CONFIG_RTL8139
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#ifndef CONFIG_PCI_PNP
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#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
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#define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
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#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
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#endif
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SCSI_AHCI
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#ifdef CONFIG_SCSI_AHCI
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#define CONFIG_SATA_ULI5288
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
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#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
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#endif /* SCSI */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define CONFIG_PIXIS_SGMII_CMD
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#define CONFIG_FSL_SGMII_RISER 1
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#define SGMII_RISER_PHY_OFFSET 0x1b
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#ifdef CONFIG_FSL_SGMII_RISER
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#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
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#endif
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC3_PHY_ADDR 2
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
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#define CONFIG_ENV_ADDR 0xfff80000
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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#endif
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_REGINFO
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_SCSI
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#define CONFIG_CMD_EXT2
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#endif
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/*
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* USB
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*/
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#define CONFIG_CMD_USB
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 16 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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/* The mac addresses for all ethernet interface */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
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#define CONFIG_HAS_ETH2
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#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
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#define CONFIG_HAS_ETH3
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#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
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#endif
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#define CONFIG_IPADDR 192.168.1.254
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#define CONFIG_HOSTNAME unknown
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#define CONFIG_ROOTPATH /opt/nfsroot
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#define CONFIG_BOOTFILE uImage
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#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
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#define CONFIG_SERVERIP 192.168.1.1
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#define CONFIG_GATEWAYIP 192.168.1.1
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#define CONFIG_NETMASK 255.255.255.0
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"perf_mode=stable\0" \
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"memctl_intlv_ctl=2\0" \
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"netdev=eth0\0" \
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"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
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"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
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"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=2000000\0" \
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"ramdiskfile=p2020ds/ramdisk.uboot\0" \
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"fdtaddr=c00000\0" \
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"fdtfile=p2020ds/p2020ds.dtb\0" \
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"bdev=sda3\0"
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#define CONFIG_HDBOOT \
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"setenv bootargs root=/dev/$bdev rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
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#endif /* __CONFIG_H */
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