mirror of
https://github.com/AsahiLinux/u-boot
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c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
293 lines
7.3 KiB
C
293 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <init.h>
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#include <net.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx35.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <fsl_pmic.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <mc9sdz60.h>
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#include <mc13892.h>
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#include <linux/types.h>
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#include <asm/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <netdev.h>
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#include <asm/mach-types.h>
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#ifndef CONFIG_BOARD_LATE_INIT
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#error "CONFIG_BOARD_LATE_INIT must be set for this board"
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#endif
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#ifndef CONFIG_BOARD_EARLY_INIT_F
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#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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u32 size1, size2;
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size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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gd->ram_size = size1 + size2;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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return 0;
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}
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#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
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static void setup_iomux_i2c(void)
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{
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static const iomux_v3_cfg_t i2c1_pads[] = {
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NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
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};
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/* setup pins for I2C1 */
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imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
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}
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static void setup_iomux_spi(void)
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{
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static const iomux_v3_cfg_t spi_pads[] = {
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MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
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MX35_PAD_CSPI1_MISO__CSPI1_MISO,
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MX35_PAD_CSPI1_SS0__CSPI1_SS0,
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MX35_PAD_CSPI1_SS1__CSPI1_SS1,
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MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
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};
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imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
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}
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#define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
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#define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
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static void setup_iomux_usbotg(void)
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{
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static const iomux_v3_cfg_t usbotg_pads[] = {
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NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
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USBOTG_OUT_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
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USBOTG_IN_PAD_CTRL),
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};
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/* Set up pins for USBOTG. */
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imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
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}
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#define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
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NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
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NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
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NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
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};
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/* setup pins for FEC */
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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int board_early_init_f(void)
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{
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struct ccm_regs *ccm =
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(struct ccm_regs *)IMX_CCM_BASE;
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/* enable clocks */
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writel(readl(&ccm->cgr0) |
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MXC_CCM_CGR0_EMI_MASK |
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MXC_CCM_CGR0_EDIO_MASK |
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MXC_CCM_CGR0_EPIT1_MASK,
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&ccm->cgr0);
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writel(readl(&ccm->cgr1) |
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MXC_CCM_CGR1_FEC_MASK |
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MXC_CCM_CGR1_GPIO1_MASK |
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MXC_CCM_CGR1_GPIO2_MASK |
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MXC_CCM_CGR1_GPIO3_MASK |
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MXC_CCM_CGR1_I2C1_MASK |
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MXC_CCM_CGR1_I2C2_MASK |
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MXC_CCM_CGR1_IPU_MASK,
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&ccm->cgr1);
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/* Setup NAND */
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__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
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setup_iomux_i2c();
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setup_iomux_usbotg();
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setup_iomux_fec();
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setup_iomux_spi();
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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static inline int pmic_detect(void)
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{
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unsigned int id;
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struct pmic *p = pmic_get("FSL_PMIC");
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if (!p)
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return -ENODEV;
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pmic_reg_read(p, REG_IDENTIFICATION, &id);
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id = (id >> 6) & 0x7;
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if (id == 0x7)
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return 1;
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return 0;
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}
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u32 get_board_rev(void)
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{
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int rev;
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rev = pmic_detect();
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return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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int board_late_init(void)
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{
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u8 val;
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u32 pmic_val;
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struct pmic *p;
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int ret;
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ret = pmic_init(I2C_0);
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if (ret)
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return ret;
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if (pmic_detect()) {
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p = pmic_get("FSL_PMIC");
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imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
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pmic_reg_read(p, REG_SETTING_0, &pmic_val);
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pmic_reg_write(p, REG_SETTING_0,
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pmic_val | VO_1_30V | VO_1_50V);
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pmic_reg_read(p, REG_MODE_0, &pmic_val);
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pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
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imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
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gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
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}
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val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
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mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
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mdelay(200);
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val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
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mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
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mdelay(200);
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val |= 0x80;
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mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
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/* Print board revision */
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printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_SMC911X)
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int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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if (rc)
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return rc;
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#endif
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return cpu_eth_init(bis);
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}
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#if defined(CONFIG_FSL_ESDHC_IMX)
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struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t sdhc1_pads[] = {
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MX35_PAD_SD1_CMD__ESDHC1_CMD,
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MX35_PAD_SD1_CLK__ESDHC1_CLK,
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MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
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MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
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MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
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MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
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};
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/* configure pins for SDHC1 only */
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imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
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esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
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return fsl_esdhc_initialize(bis, &esdhc_cfg);
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
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}
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#endif
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