mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-10-06 14:22:18 +00:00
da90d4ce38
Generalized misuse of ble within relocation and bss initialization loops caused one iteration too many. Instead of ble ('branch if lower or equal'), use blo ('branch if lower'). While we're at it, fix all 'addreee' typos. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
784 lines
17 KiB
ArmAsm
784 lines
17 KiB
ArmAsm
/*
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* armboot - Startup Code for ARM1176 CPU-core
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*
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* Copyright (c) 2007 Samsung Electronics
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*
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* Copyright (C) 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
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* 2007-09-21 - Added MoviNAND and OneNAND boot codes by
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* jsgood (jsgood.yang@samsung.com)
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* Base codes by scsuh (sc.suh)
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*/
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#include <config.h>
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#include <version.h>
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#ifdef CONFIG_ENABLE_MMU
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#include <asm/proc/domain.h>
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#endif
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#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
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#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
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#endif
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/*
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*************************************************************************
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*
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* Jump vector table as in table 3.1 in [1]
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*
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*************************************************************************
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*/
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.globl _start
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_start: b reset
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#ifndef CONFIG_NAND_SPL
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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ldr pc, _data_abort
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ldr pc, _not_used
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ldr pc, _irq
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ldr pc, _fiq
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_undefined_instruction:
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.word undefined_instruction
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_software_interrupt:
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.word software_interrupt
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_prefetch_abort:
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.word prefetch_abort
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_data_abort:
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.word data_abort
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_not_used:
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.word not_used
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_irq:
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.word irq
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_fiq:
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.word fiq
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_pad:
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.word 0x12345678 /* now 16*4=64 */
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#else
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. = _start + 64
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#endif
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.global _end_vect
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_end_vect:
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word TEXT_BASE
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/*
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* Below variable is very important because we use MMU in U-Boot.
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* Without it, we cannot run code correctly before MMU is ON.
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* by scsuh.
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*/
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_TEXT_PHY_BASE:
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.word CONFIG_SYS_PHY_UBOOT_BASE
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#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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.globl _armboot_start
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_armboot_start:
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.word _start
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#endif
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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.globl _datarel_start
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_datarel_start:
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.word __datarel_start
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.globl _datarelrolocal_start
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_datarelrolocal_start:
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.word __datarelrolocal_start
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.globl _datarellocal_start
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_datarellocal_start:
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.word __datarellocal_start
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.globl _datarelro_start
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_datarelro_start:
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.word __datarelro_start
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.globl _got_start
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_got_start:
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.word __got_start
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.globl _got_end
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_got_end:
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.word __got_end
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0, cpsr
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bic r0, r0, #0x3f
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orr r0, r0, #0xd3
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msr cpsr, r0
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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cpu_init_crit:
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/*
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* When booting from NAND - it has definitely been a reset, so, no need
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* to flush caches and disable the MMU
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*/
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#ifndef CONFIG_NAND_SPL
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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/* Prepare to disable the MMU */
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adr r2, mmu_disable_phys
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sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - TEXT_BASE)
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b mmu_disable
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.align 5
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/* Run in a single cache-line */
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mmu_disable:
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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mov pc, r2
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mmu_disable_phys:
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#ifdef CONFIG_DISABLE_TCM
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/*
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* Disable the TCMs
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*/
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mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
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cmp r0, #0
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beq skip_tcmdisable
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mov r1, #0
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mov r2, #1
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tst r0, r2
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mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
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tst r0, r2, LSL #16
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mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
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skip_tcmdisable:
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#endif
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#endif
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#ifdef CONFIG_PERIPORT_REMAP
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/* Peri port setup */
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ldr r0, =CONFIG_PERIPORT_BASE
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orr r0, r0, #CONFIG_PERIPORT_SIZE
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mcr p15,0,r0,c15,c2,4
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#endif
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/*
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* Go setup Memory and board specific bits prior to relocation.
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*/
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bl lowlevel_init /* go setup pll,mux,memory */
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/* Set stackpointer in internal RAM to call board_init_f */
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call_board_init_f:
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ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
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ldr r0,=0x00000000
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bl board_init_f
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/*------------------------------------------------------------------------------*/
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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*/
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.globl relocate_code
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relocate_code:
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mov r4, r0 /* save addr_sp */
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mov r5, r1 /* save addr of gd */
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mov r6, r2 /* save addr of destination */
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mov r7, r2 /* save addr of destination */
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/* Set up the stack */
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stack_setup:
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mov sp, r4
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adr r0, _start
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ldr r2, _TEXT_BASE
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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cmp r0, r6
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beq clear_bss
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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copy_loop:
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ldmia r0!, {r9-r10} /* copy from source address [r0] */
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stmia r6!, {r9-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo copy_loop
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#ifndef CONFIG_PRELOADER
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/* fix got entries */
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ldr r1, _TEXT_BASE /* Text base */
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mov r0, r7 /* reloc addr */
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ldr r2, _got_start /* addr in Flash */
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ldr r3, _got_end /* addr in Flash */
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sub r3, r3, r1
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add r3, r3, r0
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sub r2, r2, r1
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add r2, r2, r0
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fixloop:
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ldr r4, [r2]
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sub r4, r4, r1
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add r4, r4, r0
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str r4, [r2]
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add r2, r2, #4
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cmp r2, r3
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bne fixloop
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#endif
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#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
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#ifdef CONFIG_ENABLE_MMU
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enable_mmu:
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/* enable domain access */
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ldr r5, =0x0000ffff
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mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
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/* Set the TTB register */
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ldr r0, _mmu_table_base
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ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
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ldr r2, =0xfff00000
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bic r0, r0, r2
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orr r1, r0, r1
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mcr p15, 0, r1, c2, c0, 0
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/* Enable the MMU */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #1 /* Set CR_M to enable MMU */
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/* Prepare to enable the MMU */
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adr r1, skip_hw_init
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and r1, r1, #0x3fc
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ldr r2, _TEXT_BASE
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ldr r3, =0xfff00000
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and r2, r2, r3
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orr r2, r2, r1
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b mmu_enable
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.align 5
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/* Run in a single cache-line */
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mmu_enable:
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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mov pc, r2
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skip_hw_init:
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#endif
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clear_bss:
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#ifndef CONFIG_PRELOADER
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ldr r0, _bss_start
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ldr r1, _bss_end
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ldr r3, _TEXT_BASE /* Text base */
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mov r4, r7 /* reloc addr */
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sub r0, r0, r3
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add r0, r0, r4
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sub r1, r1, r3
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add r1, r1, r4
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mov r2, #0x00000000 /* clear */
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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bne clbss_l
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bl coloured_LED_init
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bl red_LED_on
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#endif
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/*
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* We are done. Do not return, instead branch to second part of board
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* initialization, now running from RAM.
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*/
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#ifdef CONFIG_NAND_SPL
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ldr pc, _nand_boot
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_nand_boot: .word nand_boot
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#else
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ldr r0, _TEXT_BASE
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ldr r2, _board_init_r
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sub r2, r2, r0
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add r2, r2, r7 /* position from board_init_r in RAM */
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/* setup parameters for board_init_r */
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mov r0, r5 /* gd_t */
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mov r1, r7 /* dest_addr */
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/* jump to it ... */
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mov lr, r2
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mov pc, lr
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_board_init_r: .word board_init_r
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#endif
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#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
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/*
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* the actual reset code
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*/
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0, cpsr
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bic r0, r0, #0x3f
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orr r0, r0, #0xd3
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msr cpsr, r0
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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|
*
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*************************************************************************
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*/
|
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/*
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* we do sys-critical inits only at reboot,
|
|
* not when booting from ram!
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|
*/
|
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cpu_init_crit:
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/*
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* When booting from NAND - it has definitely been a reset, so, no need
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|
* to flush caches and disable the MMU
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*/
|
|
#ifndef CONFIG_NAND_SPL
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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/* Prepare to disable the MMU */
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adr r2, mmu_disable_phys
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sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - TEXT_BASE)
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b mmu_disable
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.align 5
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/* Run in a single cache-line */
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mmu_disable:
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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mov pc, r2
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mmu_disable_phys:
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|
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#ifdef CONFIG_DISABLE_TCM
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/*
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* Disable the TCMs
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*/
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mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
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cmp r0, #0
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beq skip_tcmdisable
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mov r1, #0
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mov r2, #1
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tst r0, r2
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mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
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tst r0, r2, LSL #16
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mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
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skip_tcmdisable:
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#endif
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#endif
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|
|
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#ifdef CONFIG_PERIPORT_REMAP
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/* Peri port setup */
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ldr r0, =CONFIG_PERIPORT_BASE
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orr r0, r0, #CONFIG_PERIPORT_SIZE
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mcr p15,0,r0,c15,c2,4
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#endif
|
|
|
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/*
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* Go setup Memory and board specific bits prior to relocation.
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|
*/
|
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bl lowlevel_init /* go setup pll,mux,memory */
|
|
|
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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relocate: /* relocate U-Boot to RAM */
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adr r0, _start /* r0 <- current position of code */
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ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
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cmp r0, r1 /* don't reloc during debug */
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beq stack_setup
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ldr r2, _armboot_start
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ldr r3, _bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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add r2, r0, r2 /* r2 <- source end address */
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copy_loop:
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ldmia r0!, {r3-r10} /* copy from source address [r0] */
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stmia r1!, {r3-r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo copy_loop
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#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
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|
|
|
#ifdef CONFIG_ENABLE_MMU
|
|
enable_mmu:
|
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/* enable domain access */
|
|
ldr r5, =0x0000ffff
|
|
mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
|
|
|
|
/* Set the TTB register */
|
|
ldr r0, _mmu_table_base
|
|
ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
|
|
ldr r2, =0xfff00000
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|
bic r0, r0, r2
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orr r1, r0, r1
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mcr p15, 0, r1, c2, c0, 0
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|
|
/* Enable the MMU */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #1 /* Set CR_M to enable MMU */
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|
|
|
/* Prepare to enable the MMU */
|
|
adr r1, skip_hw_init
|
|
and r1, r1, #0x3fc
|
|
ldr r2, _TEXT_BASE
|
|
ldr r3, =0xfff00000
|
|
and r2, r2, r3
|
|
orr r2, r2, r1
|
|
b mmu_enable
|
|
|
|
.align 5
|
|
/* Run in a single cache-line */
|
|
mmu_enable:
|
|
|
|
mcr p15, 0, r0, c1, c0, 0
|
|
nop
|
|
nop
|
|
mov pc, r2
|
|
skip_hw_init:
|
|
#endif
|
|
|
|
/* Set up the stack */
|
|
stack_setup:
|
|
ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
|
|
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
|
|
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
|
|
sub sp, r0, #12 /* leave 3 words for abort-stack */
|
|
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
|
|
|
|
clear_bss:
|
|
ldr r0, _bss_start /* find start of bss segment */
|
|
ldr r1, _bss_end /* stop here */
|
|
mov r2, #0 /* clear */
|
|
|
|
clbss_l:
|
|
str r2, [r0] /* clear loop... */
|
|
add r0, r0, #4
|
|
cmp r0, r1
|
|
blo clbss_l
|
|
|
|
#ifndef CONFIG_NAND_SPL
|
|
ldr pc, _start_armboot
|
|
|
|
_start_armboot:
|
|
.word start_armboot
|
|
#else
|
|
b nand_boot
|
|
/* .word nand_boot*/
|
|
#endif
|
|
|
|
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
|
|
|
|
#ifdef CONFIG_ENABLE_MMU
|
|
_mmu_table_base:
|
|
.word mmu_table
|
|
#endif
|
|
|
|
#ifndef CONFIG_NAND_SPL
|
|
/*
|
|
* we assume that cache operation is done before. (eg. cleanup_before_linux())
|
|
* actually, we don't need to do anything about cache if not use d-cache in
|
|
* U-Boot. So, in this function we clean only MMU. by scsuh
|
|
*
|
|
* void theLastJump(void *kernel, int arch_num, uint boot_params);
|
|
*/
|
|
#ifdef CONFIG_ENABLE_MMU
|
|
.globl theLastJump
|
|
theLastJump:
|
|
mov r9, r0
|
|
ldr r3, =0xfff00000
|
|
ldr r4, _TEXT_PHY_BASE
|
|
adr r5, phy_last_jump
|
|
bic r5, r5, r3
|
|
orr r5, r5, r4
|
|
mov pc, r5
|
|
phy_last_jump:
|
|
/*
|
|
* disable MMU stuff
|
|
*/
|
|
mrc p15, 0, r0, c1, c0, 0
|
|
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
|
|
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
|
|
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
|
|
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
|
|
mcr p15, 0, r0, c1, c0, 0
|
|
|
|
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
|
|
|
mov r0, #0
|
|
mov pc, r9
|
|
#endif
|
|
|
|
|
|
/*
|
|
*************************************************************************
|
|
*
|
|
* Interrupt handling
|
|
*
|
|
*************************************************************************
|
|
*/
|
|
@
|
|
@ IRQ stack frame.
|
|
@
|
|
#define S_FRAME_SIZE 72
|
|
|
|
#define S_OLD_R0 68
|
|
#define S_PSR 64
|
|
#define S_PC 60
|
|
#define S_LR 56
|
|
#define S_SP 52
|
|
|
|
#define S_IP 48
|
|
#define S_FP 44
|
|
#define S_R10 40
|
|
#define S_R9 36
|
|
#define S_R8 32
|
|
#define S_R7 28
|
|
#define S_R6 24
|
|
#define S_R5 20
|
|
#define S_R4 16
|
|
#define S_R3 12
|
|
#define S_R2 8
|
|
#define S_R1 4
|
|
#define S_R0 0
|
|
|
|
#define MODE_SVC 0x13
|
|
#define I_BIT 0x80
|
|
|
|
/*
|
|
* use bad_save_user_regs for abort/prefetch/undef/swi ...
|
|
*/
|
|
|
|
.macro bad_save_user_regs
|
|
/* carve out a frame on current user stack */
|
|
sub sp, sp, #S_FRAME_SIZE
|
|
/* Save user registers (now in svc mode) r0-r12 */
|
|
stmia sp, {r0 - r12}
|
|
|
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
|
ldr r2, _armboot_start
|
|
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
|
|
/* set base 2 words into abort stack */
|
|
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
|
|
#else
|
|
ldr r2, IRQ_STACK_START_IN
|
|
#endif
|
|
/* get values for "aborted" pc and cpsr (into parm regs) */
|
|
ldmia r2, {r2 - r3}
|
|
/* grab pointer to old stack */
|
|
add r0, sp, #S_FRAME_SIZE
|
|
|
|
add r5, sp, #S_SP
|
|
mov r1, lr
|
|
/* save sp_SVC, lr_SVC, pc, cpsr */
|
|
stmia r5, {r0 - r3}
|
|
/* save current stack into r0 (param register) */
|
|
mov r0, sp
|
|
.endm
|
|
|
|
.macro get_bad_stack
|
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
|
/* setup our mode stack (enter in banked mode) */
|
|
ldr r13, _armboot_start
|
|
/* move past malloc pool */
|
|
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
|
|
/* move to reserved a couple spots for abort stack */
|
|
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
|
|
#else
|
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
|
#endif
|
|
|
|
/* save caller lr in position 0 of saved stack */
|
|
str lr, [r13]
|
|
/* get the spsr */
|
|
mrs lr, spsr
|
|
/* save spsr in position 1 of saved stack */
|
|
str lr, [r13, #4]
|
|
|
|
/* prepare SVC-Mode */
|
|
mov r13, #MODE_SVC
|
|
@ msr spsr_c, r13
|
|
/* switch modes, make sure moves will execute */
|
|
msr spsr, r13
|
|
/* capture return pc */
|
|
mov lr, pc
|
|
/* jump to next instruction & switch modes. */
|
|
movs pc, lr
|
|
.endm
|
|
|
|
.macro get_bad_stack_swi
|
|
/* space on current stack for scratch reg. */
|
|
sub r13, r13, #4
|
|
/* save R0's value. */
|
|
str r0, [r13]
|
|
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
|
/* get data regions start */
|
|
ldr r0, _armboot_start
|
|
/* move past malloc pool */
|
|
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
|
|
/* move past gbl and a couple spots for abort stack */
|
|
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
|
|
#else
|
|
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
|
|
#endif
|
|
/* save caller lr in position 0 of saved stack */
|
|
str lr, [r0]
|
|
/* get the spsr */
|
|
mrs r0, spsr
|
|
/* save spsr in position 1 of saved stack */
|
|
str lr, [r0, #4]
|
|
/* restore r0 */
|
|
ldr r0, [r13]
|
|
/* pop stack entry */
|
|
add r13, r13, #4
|
|
.endm
|
|
|
|
/*
|
|
* exception handlers
|
|
*/
|
|
.align 5
|
|
undefined_instruction:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_undefined_instruction
|
|
|
|
.align 5
|
|
software_interrupt:
|
|
get_bad_stack_swi
|
|
bad_save_user_regs
|
|
bl do_software_interrupt
|
|
|
|
.align 5
|
|
prefetch_abort:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_prefetch_abort
|
|
|
|
.align 5
|
|
data_abort:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_data_abort
|
|
|
|
.align 5
|
|
not_used:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_not_used
|
|
|
|
.align 5
|
|
irq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_irq
|
|
|
|
.align 5
|
|
fiq:
|
|
get_bad_stack
|
|
bad_save_user_regs
|
|
bl do_fiq
|
|
#endif /* CONFIG_NAND_SPL */
|