mirror of
https://github.com/AsahiLinux/u-boot
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cc4a0ceeac
rename CFG_NAND_LEGACY to CONFIG_NAND_LEGACY Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
387 lines
15 KiB
C
387 lines
15 KiB
C
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/***********************************************************
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* High Level Configuration Options
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* (easy to change)
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***********************************************************/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_PIP405 1 /* ...on a PIP405 board */
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/***********************************************************
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* Clock
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***********************************************************/
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_FDC
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#define CONFIG_CMD_SCSI
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_DOC
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_BSP
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#define CONFIG_NAND_LEGACY
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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/**************************************************************
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* I2C Stuff:
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* the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
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* 0x53.
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* Caution: on the same bus is the SPD (Serial Presens Detect
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* EEPROM of the SDRAM
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* The Atmel EEPROM uses 16Bit addressing.
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***************************************************************/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x53
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
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#define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
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#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
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#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
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/* 64 byte page write mode using*/
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/* last 6 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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/***************************************************************
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* Definitions for Serial Presence Detect EEPROM address
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* (to get SDRAM settings)
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***************************************************************/
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#define SPD_EEPROM_ADDRESS 0x50
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#define CONFIG_BOARD_EARLY_INIT_F
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/**************************************************************
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* Environment definitions
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**************************************************************/
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#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
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#define CONFIG_BOOTDELAY 5
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/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
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/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
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#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
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#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
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#define CONFIG_IPADDR 10.0.0.100
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#define CONFIG_SERVERIP 10.0.0.1
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#define CONFIG_PREBOOT
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/***************************************************************
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* defines if the console is stored in the environment
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***************************************************************/
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#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
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/***************************************************************
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* defines if an overwrite_console function exists
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*************************************************************/
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#define CFG_CONSOLE_OVERWRITE_ROUTINE
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#define CFG_CONSOLE_INFO_QUIET
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/***************************************************************
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* defines if the overwrite_console should be stored in the
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* environment
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**************************************************************/
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#undef CFG_CONSOLE_ENV_OVERWRITE
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/**************************************************************
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* loads config
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*************************************************************/
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MISC_INIT_R
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/***********************************************************
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* Miscellaneous configurable options
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**********************************************************/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
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#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
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#define CFG_BASE_BAUD 691200
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CFG_LOAD_ADDR 0x400000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
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#define CONFIG_PCI_PNP /* pci plug-and-play */
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/* resource configuration */
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#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
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#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFF80000
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
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#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*
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* Init Memory Controller:
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*/
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#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
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#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
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#define CONFIG_BOARD_EARLY_INIT_F
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/* Configuration Port location */
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#define CONFIG_PORT_ADDR 0xF4000000
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#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in On Chip SRAM)
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*/
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#define CFG_TEMP_STACK_OCM 1
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#define CFG_OCM_DATA_ADDR 0xF0000000
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#define CFG_OCM_DATA_SIZE 0x1000
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/***********************************************************************
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* External peripheral base address
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***********************************************************************/
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#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
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/***********************************************************************
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* Last Stage Init
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***********************************************************************/
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#define CONFIG_LAST_STAGE_INIT
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/************************************************************
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* Ethernet Stuff
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***********************************************************/
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
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/************************************************************
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* RTC
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***********************************************************/
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#define CONFIG_RTC_MC146818
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/************************************************************
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* IDE/ATA stuff
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************************************************************/
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#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
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#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
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#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
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#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
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#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
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#define CFG_ATA_REG_OFFSET 0 /* reg offset */
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#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#define CONFIG_IDE_RESET /* reset for ide supported... */
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#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
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#define CONFIG_SUPPORT_VFAT
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/************************************************************
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* ATAPI support (experimental)
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************************************************************/
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#define CONFIG_ATAPI /* enable ATAPI Support */
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/************************************************************
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* SCSI support (experimental) only SYM53C8xx supported
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************************************************************/
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#define CONFIG_SCSI_SYM53C8XX
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#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
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#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
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#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
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#define CFG_SCSI_SPIN_UP_TIME 2
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/************************************************************
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* Disk-On-Chip configuration
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************************************************************/
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#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
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#define CFG_DOC_SHORT_TIMEOUT
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#define CFG_DOC_SUPPORT_2000
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#define CFG_DOC_SUPPORT_MILLENNIUM
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/************************************************************
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* DISK Partition support
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************************************************************/
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#define CONFIG_DOS_PARTITION
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#define CONFIG_MAC_PARTITION
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#define CONFIG_ISO_PARTITION /* Experimental */
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/************************************************************
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* Keyboard support
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************************************************************/
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#define CONFIG_ISA_KEYBOARD
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/************************************************************
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* Video support
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************************************************************/
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#define CONFIG_VIDEO /*To enable video controller support */
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#define CONFIG_VIDEO_CT69000
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
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/************************************************************
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* USB support
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************************************************************/
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#define CONFIG_USB_UHCI
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#define CONFIG_USB_KEYBOARD
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#define CONFIG_USB_STORAGE
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/* Enable needed helper functions */
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#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
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/************************************************************
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* Debug support
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************************************************************/
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/************************************************************
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* support BZIP2 compression
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************************************************************/
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#define CONFIG_BZIP2 1
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/************************************************************
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* Ident
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************************************************************/
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#define VERSION_TAG "released"
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#define CONFIG_ISO_STRING "MEV-10066-001"
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#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
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#endif /* __CONFIG_H */
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