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4257f5f8f6
To make the PSCI backend more maintainable and easier to port to newer SoCs, rewrite the current PSCI implementation in C. Some inline assembly bits are required to access coprocessor registers. PSCI stack setup is the only part left completely in assembly. In theory this part could be split out of psci_arch_init into a separate common function, and psci_arch_init could be completely in C. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
66 lines
1.8 KiB
ArmAsm
66 lines
1.8 KiB
ArmAsm
/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Based on code by Carl van Schaik <carl@ok-labs.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/arch-armv7/generictimer.h>
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#include <asm/gic.h>
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#include <asm/macro.h>
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#include <asm/psci.h>
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#include <asm/arch/cpu.h>
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/*
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* Memory layout:
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*
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* SECURE_RAM to text_end :
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* ._secure_text section
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* text_end to ALIGN_PAGE(text_end):
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* nothing
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* ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
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* 1kB of stack per CPU (4 CPUs max).
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*/
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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#define GICD_BASE (SUNXI_GIC400_BASE + 0x1000)
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#define GICC_BASE (SUNXI_GIC400_BASE + 0x2000)
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@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in
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@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across
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@ this function.
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ENTRY(psci_arch_init)
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mov r6, lr
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mov r7, r0
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bl psci_get_cpu_id @ CPU ID => r0
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bl psci_get_cpu_stack_top @ stack top => r0
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sub r0, r0, #4 @ Save space for target PC
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mov sp, r0
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mov r0, r7
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mov lr, r6
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push {r0, r1, r2, ip, lr}
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bl sunxi_gic_init
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pop {r0, r1, r2, ip, pc}
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ENDPROC(psci_arch_init)
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ENTRY(psci_text_end)
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.popsection
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