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https://github.com/AsahiLinux/u-boot
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bf95d17809
Add support for Qualcomm QCS404 SoC based evaluation board. Features: - Qualcomm Snapdragon QCS404 SoC - 1GiB RAM - 8GiB eMMC, uSD slot U-boot is chain loaded by ABL in 64-bit mode as part of boot.img. For detailed build and boot instructions, refer to doc/board/qualcomm/qcs404.rst. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
81 lines
1.7 KiB
Text
81 lines
1.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm QCS404 based evaluation board device tree source
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*
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* (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
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*/
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/dts-v1/;
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#include "skeleton64.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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/ {
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model = "Qualcomm Technologies, Inc. QCS404 EVB";
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compatible = "qcom,qcs404-evb", "qcom,qcs404";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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serial0 = &debug_uart;
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};
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memory {
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device_type = "memory";
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reg = <0 0x80000000 0 0x40000000>;
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};
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soc {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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ranges = <0x0 0x0 0x0 0xffffffff>;
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compatible = "simple-bus";
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pinctrl_north@1300000 {
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compatible = "qcom,tlmm-qcs404";
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reg = <0x1300000 0x200000>;
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blsp1_uart2: uart {
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pins = "GPIO_17", "GPIO_18";
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function = "blsp_uart2";
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};
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-qcs404";
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reg = <0x1800000 0x80000>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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};
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debug_uart: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4";
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reg = <0x78b1000 0x200>;
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clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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bit-rate = <0xFF>;
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pinctrl-names = "uart";
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pinctrl-0 = <&blsp1_uart2>;
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};
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sdhci@7804000 {
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compatible = "qcom,sdhci-msm-v5";
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reg = <0x7804000 0x1000 0x7805000 0x1000>;
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clock = <&gcc GCC_SDCC1_APPS_CLK>,
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<&gcc GCC_SDCC1_AHB_CLK>;
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bus-width = <0x8>;
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index = <0x0>;
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non-removable;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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};
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};
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};
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#include "qcs404-evb-uboot.dtsi"
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