mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 01:17:39 +00:00
c7ea9612df
The assigned-clock no longer have to be dropped, the clock are now defined in clk-imx8mp.c and used by DWMAC driver to configure the DWMAC clock. Drop the workarounds from U-Boot specific DT extras. Signed-off-by: Marek Vasut <marex@denx.de>
146 lines
1.5 KiB
Text
146 lines
1.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019, 2021 NXP
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*/
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#include "imx8mp-u-boot.dtsi"
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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bootph-pre-ram;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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®_usdhc2_vmmc {
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u-boot,off-on-delay-us = <20000>;
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};
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®_usdhc2_vmmc {
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bootph-pre-ram;
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};
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&pinctrl_uart2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2_gpio {
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bootph-pre-ram;
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};
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&pinctrl_usdhc2 {
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bootph-pre-ram;
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};
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&pinctrl_usdhc3 {
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bootph-pre-ram;
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};
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&pinctrl_wdog {
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bootph-pre-ram;
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};
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&gpio1 {
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bootph-pre-ram;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&uart2 {
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bootph-pre-ram;
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};
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&crypto {
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bootph-pre-ram;
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};
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&sec_jr0 {
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bootph-pre-ram;
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};
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&sec_jr1 {
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bootph-pre-ram;
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};
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&sec_jr2 {
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bootph-pre-ram;
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};
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&i2c1 {
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bootph-pre-ram;
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};
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&i2c2 {
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bootph-pre-ram;
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};
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&i2c3 {
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bootph-pre-ram;
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};
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&i2c4 {
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bootph-pre-ram;
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};
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&i2c5 {
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bootph-pre-ram;
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};
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&i2c6 {
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bootph-pre-ram;
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};
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&usdhc1 {
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bootph-pre-ram;
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};
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&usdhc2 {
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bootph-pre-ram;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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};
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&usdhc3 {
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bootph-pre-ram;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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};
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&wdog1 {
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bootph-pre-ram;
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};
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ðphy0 {
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-delay-us = <15000>;
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reset-post-delay-us = <100000>;
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};
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&fec {
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phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <15>;
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phy-reset-post-delay = <100>;
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};
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