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fc76fa3cfa
This commit updates the .its file for the RK3399-Q7 to use the new features and demonstrates how to use those: * it marks the ATF as the 'firmware' * it tracks the OS-type for U-Boot and ATF * it loads the PMU (M0) firmware to DRAM and records the location to /fit-images (where our ATF reads it from) With the handoff of the next-stage FDT to ATF in place, we can now use this to pass information about the load addresses and names of each loadables to ATF: now we can load the M0 firmware into DRAM and avoid overwriting parts of the SPL stage. This is achieved by changing our .its-file to use an available area of DRAM as the load-address. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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|---|---|---|
| .. | ||
| fit_spl_atf.its | ||
| Kconfig | ||
| MAINTAINERS | ||
| Makefile | ||
| puma-rk3399.c | ||
| README | ||
Introduction
============
The RK3399-Q7 (Puma) is a system-on-module featuring the Rockchip
RK3399 in a Qseven-compatible form-factor.
RK3399-Q7 features:
* CPU: ARMv8 64bit Big-Little architecture,
* Big: dual-core Cortex-A72
* Little: quad-core Cortex-A53
* IRAM: 200KB
* DRAM: 4GB-128MB dual-channel
* eMMC: onboard eMMC
* SD/MMC
* GbE (onboard Micrel KSZ9031) Gigabit ethernet PHY
* USB:
* USB3.0 dual role port
* 2x USB3.0 host, 1x USB2.0 host via onboard USB3.0 hub
* Display: HDMI/eDP/MIPI
* Camera: 2x CSI (one on the edge connector, one on the Q7 specified CSI ZIF)
* NOR Flash: onboard SPI NOR
* Companion Controller: onboard additional Cortex-M0 microcontroller
* RTC
* fan controller
* CAN
Here is the step-by-step to boot to U-Boot on rk3399.
Get the Source and build ATF/Cortex-M0 binaries
===============================================
> git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
> git clone git://git.theobroma-systems.com/rk3399-cortex-m0.git
Compile the ATF
===============
> cd arm-trusted-firmware
> make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
> cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin
Compile the M0 firmware
=======================
> cd ../rk3399-cortex-m0
> make CROSS_COMPILE=arm-cortex_m0-eabi-
> cp rk3399m0.bin ../u-boot
Compile the U-Boot
==================
> cd ../u-boot
> make CROSS_COMPILE=aarch64-linux-gnu- puma-rk3399_defconfig all
Package the image
=================
Creating a SPL image for SD-Card/eMMC
> tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin spl_mmc.img
Creating a SPL image for SPI-NOR
> tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img
Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree
> make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
Flash the image
===============
Copy the SPL to offset 32k for SD/eMMC, offset 0 for NOR-Flash and the FIT
image to offset 256k card.
SD-Card
-------
> dd if=spl_mmc.img of=/dev/sdb seek=64
> dd if=u-boot.itb of=/dev/sdb seek=512
eMMC
----
rkdeveloptool allows to flash the on-board eMMC via the USB OTG interface with
help of the Rockchip loader binary.
> git clone https://github.com/rockchip-linux/rkdeveloptool
> cd rkdeveloptool
> autoreconf -i && ./configure && make
> git clone https://github.com/rockchip-linux/rkbin.git
> ./rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
> ./rkdeveloptool wl 64 ../spl_mmc.img
> ./rkdeveloptool wl 512 ../u-boot.itb
NOR-Flash
---------
Writing the SPI NOR Flash requires a running U-Boot. For the sake of simplicity
we assume you have a SD-Card with a partition containing the required files
ready.
> load mmc 1:1 ${kernel_addr_r} spl_nor.img
> sf probe
> sf erase 0 +$filesize
> sf write $kernel_addr_r 0 ${filesize}
> load mmc 1:1 ${kernel_addr_r} u-boot.itb
> sf erase 0x40000 +$filesize
> sf write $kernel_addr_r 0x40000 ${filesize}
Reboot the system and you should see a U-Boot console on UART0 (115200n8).