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https://github.com/AsahiLinux/u-boot
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d81b27a245
The woodburn board is based on the MX35 SOC. Support for both external (NOR) and internal (SD Card) boot mode are added. It uses the generic SPL framework to implement the internal boot mode. The following peripherals are supported: - Ethernet (FEC) - SD Card - NAND (512 MB) - NOR Flash In the internal boot mode, a simple imximage header is generated to set the address in internal RAM where the SOC must copy the SPL code. The initial setup is then demanded to the SPL itself. Signed-off-by: Stefano Babic <sbabic@denx.de>
137 lines
3.7 KiB
C
137 lines
3.7 KiB
C
/*
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* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <linux/types.h>
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#include <asm/arch/sys_proto.h>
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#define ESDCTL_DDR2_EMR2 0x04000000
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#define ESDCTL_DDR2_EMR3 0x06000000
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#define ESDCTL_PRECHARGE 0x00000400
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#define ESDCTL_DDR2_EN_DLL 0x02000400
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#define ESDCTL_DDR2_RESET_DLL 0x00000333
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#define ESDCTL_DDR2_MR 0x00000233
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#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
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enum {
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SMODE_NORMAL = 0,
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SMODE_PRECHARGE,
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SMODE_AUTO_REFRESH,
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SMODE_LOAD_REG,
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SMODE_MANUAL_REFRESH
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};
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#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
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static inline void dram_wait(unsigned int count)
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{
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volatile unsigned int wait = count;
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while (wait--)
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;
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}
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void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
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u32 row, u32 col, u32 dsize, u32 refresh)
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{
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struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
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u32 *cfg_reg, *ctl_reg;
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u32 val;
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u32 ctlval;
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switch (start_address) {
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case CSD0_BASE_ADDR:
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cfg_reg = &esdc->esdcfg0;
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ctl_reg = &esdc->esdctl0;
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break;
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case CSD1_BASE_ADDR:
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cfg_reg = &esdc->esdcfg1;
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ctl_reg = &esdc->esdctl1;
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break;
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default:
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return;
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}
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/* The MX35 supports 11 up to 14 rows */
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if (row < 11 || row > 14 || col < 8 || col > 10)
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return;
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ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
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/* Initialize MISC register for DDR2 */
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val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
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ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
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writel(val, &esdc->esdmisc);
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val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
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writel(val, &esdc->esdmisc);
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/*
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* according to DDR2 specs, wait a while before
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* the PRECHARGE_ALL command
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*/
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dram_wait(0x20000);
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/* Load DDR2 config and timing */
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writel(ddr2_config, cfg_reg);
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/* Precharge ALL */
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writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
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ctl_reg);
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writel(0xda, start_address + ESDCTL_PRECHARGE);
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/* Load mode */
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writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
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ctl_reg);
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writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
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writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
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writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
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writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
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/* Precharge ALL */
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writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
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ctl_reg);
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writel(0xda, start_address + ESDCTL_PRECHARGE);
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/* Set mode auto refresh : at least two refresh are required */
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writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
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ctl_reg);
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writel(0xda, start_address);
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writel(0xda, start_address);
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writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
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ctl_reg);
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writeb(0xda, start_address + ESDCTL_DDR2_MR);
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writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
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/* OCD mode exit */
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writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
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/* Set normal mode */
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writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
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ctl_reg);
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dram_wait(0x20000);
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/* Do not set delay lines, only for MDDR */
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}
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