mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
260 lines
8.2 KiB
C
260 lines
8.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
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*
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* (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
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*/
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#ifndef _CONFIG_EB_CPU5282_H_
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#define _CONFIG_EB_CPU5282_H_
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#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
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/*----------------------------------------------------------------------*
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* High Level Configuration Options (easy to change) *
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*----------------------------------------------------------------------*/
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#define CONFIG_MISC_INIT_R
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
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#define CONFIG_BOOTCOMMAND "printenv"
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/*----------------------------------------------------------------------*
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* Options *
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*----------------------------------------------------------------------*/
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#define CONFIG_BOOT_RETRY_TIME -1
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_HW_WATCHDOG
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#define STATUS_LED_ACTIVE 0
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/*----------------------------------------------------------------------*
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* Configuration for environment *
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* Environment is in the second sector of the first 256k of flash *
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*----------------------------------------------------------------------*/
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#define CONFIG_ENV_ADDR 0xFF040000
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#define CONFIG_ENV_SECT_SIZE 0x00020000
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#define CONFIG_MCFTMR
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_LOAD_ADDR 0x20000
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#define CONFIG_SYS_MEMTEST_START 0x100000
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#define CONFIG_SYS_MEMTEST_END 0x400000
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/*#define CONFIG_SYS_DRAM_TEST 1 */
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#undef CONFIG_SYS_DRAM_TEST
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/*----------------------------------------------------------------------*
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* Clock and PLL Configuration *
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*----------------------------------------------------------------------*/
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#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
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/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
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#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
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#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
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/*----------------------------------------------------------------------*
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* Network *
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*----------------------------------------------------------------------*/
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#define CONFIG_MCFFEC
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#define CONFIG_MII 1
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#define CONFIG_MII_INIT 1
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#define CONFIG_SYS_DISCOVER_PHY
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#define CONFIG_SYS_RX_ETH_BUFFER 8
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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#define CONFIG_SYS_FEC0_PINMUX 0
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#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
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#define MCFFEC_TOUT_LOOP 50000
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*-------------------------------------------------------------------------
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*-----------------------------------------------------------------------*/
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#define CONFIG_SYS_MBAR 0x40000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*-----------------------------------------------------------------------*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE0 0x00000000
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#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
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#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
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#define CONFIG_SYS_MONITOR_LEN 0x20000
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
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#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
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#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
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#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
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CF_CACR_CEIB | CF_CACR_DBWE | \
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CF_CACR_EUSP)
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/*-----------------------------------------------------------------------
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* Memory bank definitions
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*/
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#define CONFIG_SYS_CS0_BASE 0xFF000000
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#define CONFIG_SYS_CS0_CTRL 0x00001980
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#define CONFIG_SYS_CS0_MASK 0x00FF0001
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#define CONFIG_SYS_CS2_BASE 0xE0000000
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#define CONFIG_SYS_CS2_CTRL 0x00001980
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#define CONFIG_SYS_CS2_MASK 0x000F0001
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#define CONFIG_SYS_CS3_BASE 0xE0100000
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#define CONFIG_SYS_CS3_CTRL 0x00001980
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#define CONFIG_SYS_CS3_MASK 0x000F0001
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/*-----------------------------------------------------------------------
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* Port configuration
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*/
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#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
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#define CONFIG_SYS_PADDR 0x0000000
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#define CONFIG_SYS_PADAT 0x0000000
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#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
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#define CONFIG_SYS_PBDDR 0x0000000
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#define CONFIG_SYS_PBDAT 0x0000000
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#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
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#define CONFIG_SYS_PCDDR 0x0000000
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#define CONFIG_SYS_PCDAT 0x0000000
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#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
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#define CONFIG_SYS_PCDDR 0x0000000
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#define CONFIG_SYS_PCDAT 0x0000000
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#define CONFIG_SYS_PASPAR 0x0F0F
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#define CONFIG_SYS_PEHLPAR 0xC0
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#define CONFIG_SYS_PUAPAR 0x0F
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#define CONFIG_SYS_DDRUA 0x05
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#define CONFIG_SYS_PJPAR 0xFF
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/*-----------------------------------------------------------------------
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_SYS_FSL_I2C_SPEED 100000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0
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#ifdef CONFIG_CMD_DATE
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#define CONFIG_RTC_DS1338
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#define CONFIG_I2C_RTC_ADDR 0x68
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#endif
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/*-----------------------------------------------------------------------
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* VIDEO configuration
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*/
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_VCXK 1
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#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
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#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
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#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
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#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001
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#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT
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#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR
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#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002
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#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT
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#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR
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#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004
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#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE
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#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE
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#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2
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#endif /* CONFIG_VIDEO */
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#endif /* _CONFIG_M5282EVB_H */
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/*---------------------------------------------------------------------*/
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